Special Symposium: CHIPS R&D — Challenges and Opportunities

CHIPS

Submit your Poster Only Abstract - due March 31

Please first review the information for authors — abstract submission guidelines.

Symposium Co-Chairs

Dalia Yablon
Technical Program Chair
TechConnect World Innovation Conference

Alex Norman
Executive Director
Princeton Institute of Materials

R. Joseph Kline
Project Leader
National Institute of Standards and Technology

Key Speakers

In-Line Metrology Requirements and Needs for Leading Edge Technology
Daniel Schmidt
Metrology Engineer, IBM Research

CHIPS Act Semiconductor Metrology Needs for R&D
David Henshall
VP of Business Development, SRC

Semiconductor manufacturing for meta-optics
Wei Ting Chen
Founder, SNOChip

Solutions for Gate-all-around (GAA) Device Development and Manufacturing
Xiaoting Gu
Senior Manager, Thermo Fisher Scientific

The role of academia in the future of semiconductor manufacturing
Daniel Lopez
Professor, The Pennsylvania State University

Mitigating challenges in high resolution imaging and electrical failure analysis for advanced semiconductor devices
Sandip Basu
Product Marketing Manager, Zeiss Microscopy

3DHI in Geiger-mode Avalanche Photodiode Arrays
David Hill
Senior Research Scientist, SRI International

Marla Dowell
Director
NIST

With passage of the 2022 CHIPS for America Act, the US government is making a $50 billion investment to catalyze long-term growth in the domestic semiconductor industry in support of US national and economic security. A significant portion of this funding - $11 billion – goes towards R&D initiatives to create a network of innovation in the US semiconductor ecosystem.

This symposium will focus on 3 target areas identified as critical to the R&D initiatives:

Metrology and characterization needs for leading-edge CMOS and beyond CMOS technologies including 3D devices for logic and memory
Measurements for advanced packaging/3D heterogeneous integration
Material purity and quality – requirement and challenges for the semiconductor industry as contamination and purity standards continue to become more strict.

*This symposium gathers experts to discuss research challenges and opportunities associated with the recently passed CHIPS act, but it is not an official activity by or related to the US CHIPS office.

Back to Top ↑ 2023 Symposium Sessions
1:30	CHIPS: Current Challenges and New Solutions to Boost Domestic Chips Manufacturing I
	Tuesday June 20
10:30	CHIPS: Current Challenges and New Solutions to Boost Domestic Chips Manufacturing II
1:30	CHIPS: Advanced Metrology to Ensure Success for Next Generation Semiconductors
	Wednesday June 21
9:00	CHIPS: Advances in Packaging for New Chips Innovation

2023 Symposium Program
	Monday June 19

1:30	CHIPS: Current Challenges and New Solutions to Boost Domestic Chips Manufacturing I	TBA
	Session chair: Joe Kline, National Institute of Standards & Technology, US
	Mitigating challenges in high resolution imaging and electrical failure analysis for advanced semiconductor devices S. Basu, Zeiss, US
	Semiconductor manufacturing for meta-optics W.T. Chen, SNOChip, US
	Vulnerability of In-Memory Compute to Hardware Trojans: A Case Study using Two-dimensional Memtransistor A. Wali, H. Ravichandran, S. Das, Pennsylvania State University, US
	Critical Materials for Critical Goods: Rebuilding the Microelectronics Industrial Base A.N. Caruso, Midwest Microelectronics Collective, US
	A Novel Photonic Switching Device K. Sampayan, S. Sampayan, Opcondys, Inc., US
	Tuesday June 20

10:30	CHIPS: Current Challenges and New Solutions to Boost Domestic Chips Manufacturing II	TBA
	Session chair: Alex Norman, Princeton University, US
	TBA TBA, Office of Science and Technology Policy, US
	The role of academia in the future of semiconductor manufacturing D. Lopez, Pennsylvania State University, US
	TBA M. Dowell, National Institute of Standards and Technology, US

1:30	CHIPS: Advanced Metrology to Ensure Success for Next Generation Semiconductors	TBA
	Session chair: Alex Norman, Princeton University, US
	In-Line Metrology Requirements and Needs for Leading Edge Technology D. Schmidt, IBM Research, US
	Solutions for Gate-all-around (GAA) Device Development and Manufacturing X. Gu, P. Hsu, Y.H. Kim, A. Mani, P. Kirby, Thermo Fisher Scientific, US
	CHIPS Act Semiconductor Metrology Needs for R&D D. Henshall, V. Zhirnov, T. Younkin, Semiconductor Research Corporation (SRC), US
	Surface and subsurface quantitative mechanical property measurements by contact resonance atomic force microscopy on low-k dielectric structures G. Stan, C.V. Ciobanu, S.W. King, National Institute of Standards and Technology, US
	Analysis of buried interfaces for device technology by soft and hard X-ray photoemission K. Artyushkova, J. Mann, S. Zaccarine, Physical Electronics, US
	Evaluating the Impact of Defects, Interfaces and Boundaries on Thermal Transport in 2D Materials Using a Novel Opto-Thermal Metrology Technique with Sub-Micron Resolution B.M. Foley, A.H. Jones, J.T. Gaskins, P.E. Hopkins, Laser Thermal Inc, US
	Wednesday June 21

9:00	CHIPS: Advances in Packaging for New Chips Innovation	TBA
	Session chair: Joe Kline, National Institute of Standards and Technology, US
	3DHI in Geiger-mode Avalanche Photodiode Arrays D. Hill, J. Zhu, W. Chan, S. Griggs, N. Park, SRI International, US
	Novel, Robust Anisotropic Conductive Epoxy Technology for Advanced Semiconductor Packaging Applications M. Ramkumar, SunRay Scientific Inc., US
	What’s Missing in Your Cure Kinetics Model for Advanced Epoxy Molding Compounds? R. Tao, S.P. Phansalkar, C. Kim, A.M. Forster, B. Han, National Institute of Standards and Technology, US
	Densely Packed Electronic Systems P. Salmon, Electronic Innovations, allied with Nif/t,LLC, US
	GaN FinFET 3DHI Microsystems B. Lu, Finwave Semiconductor, Inc., US
	Enabling a circular economy of semiconductor process gases through Metal-Organic Frameworks (MOFs) M.H. Weston, NuMat Technologies, US