Solutions for Gate-all-around (GAA) Device Development and Manufacturing

X. Gu, P. Hsu, Y.H. Kim, A. Mani, P. Kirby
Thermo Fisher Scientific,
United States

Keywords: gate-all-around, CMOS, metrology, defect localization, failure analysis


Gate-all-around (GAA) transistor technology is the next inflection point for complimentary metal-oxide semiconductor (CMOS) logic devices scaling beyond the 5nm node. For advanced logic developers and manufacturers, GAA structures have introduced new metrology, defect localization, and failure analysis challenges at leading edge semiconductor fabs and labs that may impact time-to-market and manufacturing yields. Many of these challenges are a direct result of the complexity and three-dimensional (3D) nature of the GAA structure. For example: • GAA transistor technology requires several key modules in the front-end-of-line (FEOL) process. This increases the number of process steps, requiring precise control of the critical dimensions (CDs) of these FEOL modules at the atomic scale level. An additional complication is CDs are often hidden in complex 3D structures hindering the ability to accurately measure CDs with current fab metrology solutions, such as optical critical dimension (OCD) and top-down CD-SEM due to their resolution or information depth limitations. To overcome the limitations of current fab metrology solutions, a higher volume of high-quality transmission electron microscopy (TEM) metrology data becomes necessary for faster process development and yield improvement. • GAA device complexity creates a number of defect localization challenges with faults in the 3D structure potentially resulting in device failure and yield loss. Three types of defects that semiconductor fabs are encountering are surface/near-surface physical defects, buried physical defects, and electrical defects. Of these, the most challenging type is buried physical defects, which are not easily located with current fab inspection tools during FEOL process due to the lack of electrical information. As waiting until the back-end-of-line (BEOL) process to localize and analyze these defects results in increased time loss and production costs, atomic-scale characterization of the buried physical defects’ root cause is essential during the FEOL process. • GAA scaling in the FEOL process requires innovations on the redesign of power distribution, including both inserting buried power rail (BPR) in the FEOL process and relocating power distribution network (PDN) to the backside of the wafers. While the backside PDN provides benefits for device performance, it also creates unique challenges for fault localization and analysis with metal interconnects on both sides of the transistors. To pinpoint the failure deeply hidden in device structure, several steps from electrical failure analysis (EFA) to physical failure analysis (PFA) need to be cautiously taken to remove materials without damaging circuits. Addressing this challenge requires a unique approach to effectively perform fault localization workflows. This session will provide an overview of GAA challenges, from the FEOL transistor manufacturing to the BEOL PDN design, and information on metrology, defect localization, and failure analysis solutions. Workflow solutions will be elaborated on in detail to assist semiconductor fabs as they strive to achieve a higher manufacturing yield and bring GAA technology to the market faster.