Mitigating challenges in high resolution imaging and electrical failure analysis for advanced semiconductor devices

S. Basu
United States

Keywords: chips, microelectronics, semiconductors, supply chain, materials


As semiconductor devices become smaller, faster and more complex, IC designers have adopted 3D architectures having high interconnect density and implemented novel materials. The development, characterization and failure analysis of these nanoscale devices require advanced instrumentation and techniques for imaging and analysis. For high resolution electron microscope measurements it is critical to ensure that the device and any defect are not damaged or electrically altered by the electron beam. At ZEISS, one of the ways we try to mitigate these challenges is with excellent scanning electron microscope performance at low accelerating voltages and currents. In this presentation we will discuss a few examples of how the surface sensitive imaging and superior passive voltage contrast enables not only differentiating between different layers at nanoscale, but also easy integration of reliable and repeatable measurements with nanoprobing, AFM, EDS and STEM for materials analysis.