Scaling Chiplet Integration Through Advances in Printed Interconnects

N. Frick, M. Fisher and C. Contreras Sepulveda
North Carolina State University,
United States

Keywords: dense interconnects, chiplet bridge, silicon via


As the semiconductor industry continues to pursue advanced chiplet packaging for larger and more complex dies, innovative interconnect solutions are needed to enable high-volume manufacturing. This presentation will overview recent progress in printed dense interconnect technologies that promise fine-pitch routing down to 2 μm lines/spaces. By leveraging high-resolution printing techniques traditionally used for flat panel display manufacturing, these interconnect methods can facilitate cost-effective heterogeneous 3D integration. Specifically, this project will describe novel approaches for scalable printed redistribution layer fabrication using advanced printing techniques. We will showcase test vehicles and characterization data demonstrating precise overlay alignment, low contact resistance, high conductor density, and compatibility with Chip-to-Wafer and Wafer-to-Wafer stacking integration flows. These printed interconnect technologies could provide a customizable foundation for billion-unit production of chiplets across logic, memory, analog/RF, sensor, and optical dies. Looking forward, we will outline the potential impacts that reliable interconnect scaling has on chiplet technology for AI acceleration, exascale computing, and advanced system-on-chip realizations.