TSMC Corporate Research,
Summary:Low dimensional 1D carbon nanotubes hold promise as candidate channel materials for highly scaled and high performance transistors beyond the limits of Silicon-based transistors. This talk will first motivate transistors built on low-D channels due to the significant speed, energy efficiency, and transistor density benefits enabled by their electronic and physical properties. Next, single-CNT FET experimental studies are utilized for insight into the quality and operating principles of device component modules including (1) low resistance N- and P- contacts down to 10 nm contact length, (2) high-capacitance gate dielectrics optimized for deposition on SP2 carbon surfaces to enable electrostatic control down to 15 nm gate length, and (3) controlled N- and P- remote dielectric doping to engineer device resistance. To achieve high current density each transistor must contain multiple CNTs as the channel, therefore we will review state-of-the-art strategies to assembly densely aligned arrays of CNT with controlled CNT spacing between 2-10 nm and uniform electronic bandgap. The final portion of the talk will highlight recent advances from our team to integrate the best device components together to demonstrate high performance CNT MOSFETs. A summary of remaining challenges and device design tradeoffs will help to give clear direction for future studies.