Aligned Arrays of Carbon Nanotubes with High Semiconducting Purity for Integrated Circuits

J Provine, Y. Yemane
Aligned Carbon,
United States

Keywords: CNFET, carbon nanotubes, CNT purification


The computation demands for future abundant data applications will far exceed the capabilities of today’s systems because silicon CMOS scaling has hit fundamental limits in power as well as architectural limits in memory access time. Heterogenous integration of various types are becoming commercially available, but the industry's roadmap for future computing targets monolithic 3D integration to achieve ultimate performance in data intensive computation. Carbon nanotubes (CNTs) have interest as the semiconducting material for transistor channels which can be integrated monolithically on existing silicon circuitry. They do not have the same thermal budget limitations of silicon or III-V semiconductor fabrication processes. Key to this development is high volume compatible manufacturing of CNTs that are both aligned and purified to select only the semiconducting CNTs. This combination has proved elusive to date. Aligned Carbon will report on their development of a scalable purification process which can preserve the alignment of CNT arrays through the selective removal of metallic CNTs. Purity is validated from the performance of large suites of CNT field effect transistors (CNFETs) each containing several aligned CNTs. Additionally, aligned CNT synthesis and CNT integration in to wafer fabrication processes will be discussed.