Cryo-CMOS Modeling for Quantum Computing Applications

X. Chen, H. Elgabra, L. Wei
University of Waterloo,
Canada

Keywords: MOSFET, cryogenic temperature, virtual-source model, noise model

Summary:

Practical quantum computers require the integration of a large number of qubits, e.g., in the thousands and millions, to overcome the fragility of the quantum states. Those qubits reside in extremely low temperatures (e.g. tens of mK) and demand a high degree of integration, low noise, and low power consumption for the control and read-out electronics. Standard CMOS technologies at cryogenic temperatures (cryo-CMOS) are experimentally verified to perform well and poised to be the best solution for the scalability problem for quantum computing. The lack of mature device compact models at cryogenic temperatures (cryo-T) is a major roadblock to design cryo-CMOS electronics. In this work, we demonstrate a compact model that accurately captures the current-voltage behavior of MOSFETs over a wide range of temperatures across different technologies. The model is based on the MIT Virtual Source model that features good accuracy with a small number of device parameters. Special consideration is given to the subthreshold swing parameter (SS), which would be proportional to kT/q if following the prediction of RT models. Experimental results show that SS decreases only by a factor less than 10 between 300K and 4K, defying the temperature proportionality. An improved expression for the SS parameter is proposed to capture the experimental behavior. Low-noise operation is a big concern of the control and readout circuits for qubits. Fortunately, thermal noise from the resistances (4kT/R) in the circuits is greatly reduced at cryo-T. However, the biggest noise source in the MOSFETs, namely the channel noise Sid, does not scale with temperature as suggested by the experimental results. This goes against the thermal-noise based estimations for cryo-CMOS noise performance. We propose a shot-noise based model for the MOSFET channel noise that is temperature insensitive and agrees well with the experimental results. Based on this model, the channel noise does not scale with temperature, but mainly depends on the drain current. An approach to verify the temperature scalability of the MOSFET channel noise is to measure the phase noise of ring oscillators at different temperatures. The 1/f2 region in its phase noise spectrum mainly comes from the channel noise of individual transistors. When we normalize the phase noise to the offset frequency f and center frequency f0, the resulting quantity becomes only dependent on the transistor channel noise and current. We measured the normalized phase noise of a ring oscillator in 65-nm CMOS process with 197 stages of inverters at 300K, 77K and 4K. If the thermal noise assumption for the channel noise holds, the phase noise at 4K would improve by around 19 dB (75x) compared to those at 300K at the same current densities. On the contrary, we observed no significant difference for phase noise between the three vastly different temperatures. The results strongly suggest that the MOSFET channel noise does not scale with temperature.