Monolithic III-V/Si Technology Co-integration and Hybrid Circuit Co-design

X. Zhou, S.B. Chiah, B. Syamal
Nanyang Technological University,
Singapore

Keywords: CMOS, HEMT, III-V, LED, monolithic integration, process design kit (PDK)

Summary:

Historically, it is the invention of monolithic integration of transistors in the planar process, not the wire-bonded version of the integrated-circuit (IC) invention, which created the IC industry in the past half a century. Today, even with extreme high degree of integration for system-on-chip (SoC) in Si technology, input/output (I/O) and power modules are primarily separate chips in III/V technology “wire-bonded” to Si chips in a high-tech product. There is a strong incentive and trend toward monolithic III-V/Si integration for future heterogeneous SoC as the conventional Si-SoC is running towards its limit. Singapore-MIT Alliance for Research and Technology’s Low Energy Electronic Systems (SMART-LEES) research program is such an endeavor to embark on monolithic III-V/Si technology co-integration and hybrid circuit co-design. With its double-layer bond-and-transfer (DL-BaT) process, we have demonstrated III-V devices co-integrated with Si devices in a single chip in 200-mm Si-foundry process. In this paper, we present an overview of the SMART-LEES program and a demonstration of III-V/Si co-integrated chip, with light-emitting diode (LED) with Si-CMOS drivers and GaN-HEMT/Si-MOSFET monolithic cascade module as examples. These monolithic heterogeneous circuit cells are designed with hybrid III-V/Si process design kit (PDK) augmented from Si-foundry PDK. We show that the key to realizing monolithic heterogeneous integration is to have a hybrid PDK with consistent III-V and Si device compact models for future monolithic III-V/Si IC chip design with high-frequency, high-power, as well as optical devices in a single design environment.