F.M. Puglisi, T. Zanotti, P. Pavan
Università di Modena e Reggio Emilia,
Keywords: resistive memory, Verilog-A, neuromorphic, logic-in-memory, compact model, random telegraph noise, variability
Summary:The increasing adoption of artificial intelligence (AI) algorithms in our daily life is demanding more energy efficient hardware designs. Particularly, the computation performed by edge devices has stringent energy requirements due to portability. In ordinary computing architectures, most of the time and energy inefficiencies are caused by the von Neumann bottleneck, which arises due to the necessity to transfer data between the memory, where data are stored, and the CPU, where data are processed. Therefore, in recent years, considerable effort has been devoted to developing non-von Neumann architectures, i.e. bringing the computation capabilities closer to where the data are stored, up to the point where the computation is performed directly inside the memory. Among emerging nanotechnologies, Resistive Random Access Memory (RRAM) is promising in enabling in-memory computation, providing sub-ns switching speed and device scalability beyond CMOS limitations. The practical exploitation of such devices in Logic-in-Memory solutions and/or in neuromorphic hardware strongly requires dependable compact models for reliable circuit simulations with predictive capabilities. In this framework, we propose a physics-based compact model of the Resistive Random Access Memory (RRAM) device. The detailed understanding of the device physics and of the role played by defects, achieved by using self-consistent physics simulations based on a multi-scale approach, is exploited to derive a set of compact equations describing the device switching in different operating conditions, including also the effects of cycling variability. The effect of Random Telegraph Noise (RTN), which constitutes an additional variability source, is also included in the compact model by means of a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. This allows performing transient simulations including the effect of RTN also in its multilevel form (due to the concurrent action of many defects). Importantly, the role of temperature and of self-heating is self-consistently included in the model in a dynamic fashion which allows accurate predictions also when using very short pulses. The compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data from different RRAM technologies reported in the literature. Specifically, we show how both DC and ultra-fast pulsed experimental data can be reproduced using a single set of parameters. In addition, we show how the model enables advanced circuit simulations for many emerging applications. Particularly, we demonstrate how the model can be used to i) design and evaluate the performance of a logic-in-memory circuit architecture implementing a 1-bit full-adder accounting for the intrinsic variability of the resistive states and the logic state degradation, and ii) account for the spike-timing dependent plasticity features, useful for neuromorphic circuits.