U. Radhakrishna, A. Zubair, M. Theng, T. Palacios, D. Antoniadis
Massachusetts Institute of Technology,
Keywords: FEFET, NCFET, MVSNC, neuromorphic devices
Summary:This work presents a new comprehensive physics-based compact Verilog-A model, the MIT Virtual Source Negative Capacitance FET (MVSNC) model that describes transistors with ferroelectric (FE)-oxides in their gate-stack. The model combines the concept of virtual-source carrier-charge-injection for the computation of channel-current and charges in the underlying baseline transistor together with the Landau-Khalatnikov (L-K) equation or Preisach model to capture the polarization switching characteristics of the FE-oxide. The model provides a framework to evaluate novel device ideas and their impact at the system-level application stage, which is particularly timely due to the recent surge in interest in the application of doped HfO2 ferroelectric-transistors for logic, radio-frequency (RF) and neuromorphic applications. The model calibrated against device-measurements is used for two example case studies: (i) to evaluate the design principles and performance capabilities of Negative Capacitance FETs (NCFETs) optimized for high frequency (RF and mm-wave) applications and (ii) to test the scalability of FeFET analog synapses, provide improved device-design, and assess the impact of device-performance on the system-level learning performance in a multilayer perceptron neural network layer simulation.