Frequency to Digital Converter

X. Liu, T. Ytterdal, M. Shur
Rensselaer Polytechnic Institute,
United States

Keywords: terahertz, frequency to digital converter, SPICE, unified charge control model, Si MOS


Our simulation using advanced terahertz (THz) compact SPICE model shows that Si MOS fabricated using standard VLSI technology with feature sizes ranging from 20 nm to 130 nm could enable a Frequency to Digital Converter (FDC) operating in the terahertz (THz) frequency range. The FDC is using THz spectrometers with the identical magnitude but phase shifted THz signals applied between gate-source and gate-drain of Si MOS transistors of different feature sizes tunable by the gate or back bias. Such a system could use broadband phase-shifted antennas connected to the source and drain of each transistor. Comparators are used to assign the digital values to the frequencies measured by the Si MOS spectrometers. The simulation models are based on the unified charge control model for FETs accounting for the electron inertia effect and the distributed channel resistances, capacitances and Drude inductances. In the THz range of frequencies, the channel is modeled as a nonlinear transmission line being split into multiple segments. Each segment includes the segment resistance, two gate-to-channel capacitances and the Drude inductance. For example, an accurate simulation of the 130 nm Si MOS at 300 GHz requires at least 14 sections. The compact multi-segment model has been implemented in ADS, Spectre and AIM-Spice. The modeling results are validated by comparing the calculated current-voltage and capacitance voltage characteristics with the measured data and TCAD simulation results. Si MOS with different feature sizes operating as the THz spectrometers support the frequency range 0.1 THz to 4 THz by varying the gate length from 20 nm to 500 nm. Our simulations show that the THz FDC using THz spectrometers could be also implemented in other materials systems including AlGaN/GaN, AlGaAs/InGaAs, and p-diamond. However, the implementation in Si CMOS technology is sufficiently robust and might be more practical and economical.