2018 Workshop on

Compact Modeling

WCM 2018

WCM - Compact Modeling

Symposium Chair

Xing Zhou
Professor
Nanyang Technological University

Key Speakers

Hybrid Process Design Kit: Single-Chip Monolithic III-V/Si Cascode GaN-HEMT
Siau Ben Chiah
Senior Research Fellow, Centre for Micro-/Nano-electronics, Nanyang Technological University, Singapore

ASM-HEMT: A Robust Physics-Based GaN HEMT Model for Power and RF Applications
Sudip Ghosh
Indian Institute of Technology, Kanpur, India

Single Protonic Phonon Absorption Limited Bipolar and Unipolar Trappy Proton Transport in Pure Liquid Water Modeled by Melted Ice Lattice
Binbin Jie
Department of Physics, Xiamen University, China

Atomic model for Negative Capacitance FET
Gengchiau Liang
National University of Singapore, Singapore

Michael Schröter
University of Technology Dresden, Germany

Physics-based MIT Virtual Source Negative Capacitance FET model (MVSNC): Circuit-Performance Evaluation of NCFETs under Dielectric Leakage Scenarios
Ujwal Radhakrishna
Postdoctoral Research Associate, Research Laboratory of Electronics, Massachusetts Institute of Technology

Unified Compact Model for Gate All Around FETs- Nanosheets, Nanowires, Multi Bridge Channel MOSFETs
Pragya Kushwaha
Postdoctoral Research Associate, University of California, Berkeley

Experiment and Model for Distance-Dependent Mismatch
Ning Lu
Senior Engineer, IBM Systems

Symposium Sessions
	Tuesday May 15
9:00	Workshop on Compact Modeling (WCM) - Water Physics & Atomic Model
10:30	WCM - Virtual Source Model & SiC Model
1:30	WCM - GaN-HEMT Models & PDK
3:30	WCM - Models for GAA, RRAM, TFT & Mismatch

Symposium Program
	Tuesday May 15

9:00	Workshop on Compact Modeling (WCM) - Water Physics & Atomic Model	262 A
	Session chair: Ujwal Radhakrishna, MIT, US
9:00	Single Protonic Phonon Absorption Limited Bipolar and Unipolar Trappy Proton Transport in Pure Liquid Water Modeled by Melted Ice Lattice (invited presentation) B. Jie, C. Sah, Xiamen University, CN
9:30	Atomic model for Negative Capacitance FET (invited presentation) G. Liang, National Unoversity of Singapore, SG

10:30	WCM - Virtual Source Model & SiC Model	262 A
	Session chair: Binbin Jie, Xiamen University, CN
10:30	Physics-based MIT Virtual Source Negative Capacitance FET model (MVSNC): Circuit-Performance Evaluation of NCFETs under Dielectric Leakage Scenarios (invited presentation) U. Radhakrishna, MIT, US
11:00	A Compact Model for SiC Junction Barrier Schottky Diode for High-Voltage and High-Temperature Applications (invited presentation) D. Navarro, F. Herrera, M. Miura-Mattausch, H.J. Mattausch, M. Takusagawa, J. Kobayashi, M. Hara, Hiroshima University, JP
11:30	Flexible virtual source compact model for fast modeling of new channel materials and device architectures (invited presentation) F. Wolf, S. Mothes, M. Schröter, TU Dresden, DE

1:30	WCM - GaN-HEMT Models & PDK	262 A
	Session chair: Ning Lu, IBM, US
1:30	Hybrid Process Design Kit: Single-Chip Monolithic III-V/Si Cascode GaN-HEMT (invited presentation) S.B. Chiah, X. Zhou, K.E.K. Lee, D. Antoniadis, E.A. Fitzgerald, Nanyang Technological University, SG
2:00	ASM-HEMT: Industry Standard GaN HEMT Model for Power and RF Applications (invited presentation) S. Ghosh, S.A. Ahsan, S. Khandelwal, A. Pampori, R. Dangi, Y.S. Chauhan, IIT Kanpur, IN
2:30	Analytical Surface Potential Solution for Low Effective Mass Channel Common Double Gate MOSFET A.S. Chakraborty, S. Jandhyala, S. Mahapatra, Indian Institute of Science, Bangalore, IN

3:30	WCM - Models for GAA, RRAM, TFT & Mismatch	262 A
	Session chair: Xing Zhou, Nanyang Technological University, SG
3:30	Unified Compact Model for Gate All Around FETs- Nanosheets, Nanowires, Multi Bridge Channel MOSFETs (invited presentation) P. Kushwaha, J.P. Duarte, Y-K. Lin, H. Agarwal, H-L. Chang, A. Sachid, S. Salahuddin, Y.S. Chauhan, C. Hu, University of California Berkeley USA, US
4:00	Analysis, Compact Modelling and Characterisation of Devices with Hysteresis, Memresistance and Snapback (invited presentation) T. Wang, J. Roychowdhury, University of California, Berkeley, US
4:30	Experiment and Model for Distance-Dependent Mismatch (invited presentation) N. Lu, N. Zamdmer, R. Wachnik, IBM, US
5:00	A Predictive Resistive RAM Compact Model with Synaptic Behavior for Circuit Simulations J.W. Lee, C.-H. Hsu, M.H. Chiang, National Cheng Kung University, TW
5:20	A turn‐on DC surface‐potential‐based drain current model for fully‐depleted poly‐Si thin film transistors Z. Zhu, J. Chu, Suzhou Vocational University, CN

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM), now celebrating it's 14th year, was one of the first of its kind in bringing people in the CM field together.The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:

Intrinsic Models
- Bulk MOSFET
- SOI MOSFET (partial-/full-depletion)
- Multiple-Gate FET (DG/TG/GAA)
- High-Voltage/LDMOS
- Thin-Film Transistor (TFT)
- Schottky-Barrier/Tunneling/Junctionless FET (SB-FET/JLFET/TFET)
- Bipolar/Junction (BJT/HBT/SiGe/JFET)
- HEMT (GaN/InGaP/InGaAs)
- Non-quasi-static
- RF
Extrinsic/Interconnect Models
- Parasitic elements
- Passive device
- Diode
- Resistor
- ESD
- Interconnect
Atomic/Quantum Models
- Ballistic device
- Carbon-Nanotube/Graphene FET (CNFET/GFET)
- Organic FET
Statistical Variability/Reliability/Noise Models
- Statistical variability
- Reliability/hot carrier
- Mismatch
- Noise
Multi-Level Models
- Subcircuit model
- Gate/block model
- Behavioral model
- Numerical/TCAD/table-based
Model Extraction and Interface
- Parameter extraction and optimization
- Model-simulator interface
- Model standardization
- Model development platform
- Verilog-A

The confirmed invited speakers are listed below:

Siau Ben Chiah, Nanyang Technological University, Singapore
Sudip Ghosh and Yogesh Chauhan, IIT Kanpur, India
Binbin Jie and Chihtang Sah, Xiamen University, China
Pragya Kushwaha and Chenming Hu, UC Berkeley, USA
Gengshiau Liang, National University of Singapore, Singapore
Dondee Navarro and Mitiko Miura-Mattausch, Hiroshima University, Japan
Ujwal Radhakrishna and Dimitri Antoniadis, Massachusetts Institute of Technology, USA
Michael Schröter, University of Technology Dresden, Germany
Tianshi Wang and Jaijeet Roychowdhury, UC Berkeley, USA
Ning Lu, Senior Engineer, IBM Systems, USA