Analysis, Compact Modelling and Characterisation of Devices with Hysteresis, Memresistance and Snapback

T. Wang, J. Roychowdhury
University of California, Berkeley,
United States

Keywords: memristor, ESD, compact model, hysteresis, snapback, Verilog-A, homotopy


Hysteresis is the dependence of a device's response on not only its instantaneous input, but also the input's history. It is an essential property of many devices --- the characteristic pinched I-V curves of memristors make them suitable for data storage; the snapback behavior in ESD clamps determines the protection effectiveness. Existing models for such devices usually use if-else statements, discontinuous functions, Boolean variables in their equations, or attempt to modify time integration methods internally. As a result, they perform poorly in simulation. In this work, we properly study the nonlinear dynamics that generate the hysteretic behaviour, then design compact models for such devices that are continuous, smooth and mathematically well posed, We also discuss the techniques for determining the model parameters. Through the process, we highlight the use of open-source tools --- Berkeley MAPP and VAPP --- for prototyping and debugging the models, as well as advanced simulation algorithms --- homotopy and periodic steady state analyses --- for model characterisation.