P. Kushwaha, J.P. Duarte, Y-K. Lin, H. Agarwal, H-L. Chang, A. Sachid, S. Salahuddin, Y.S. Chauhan, C. Hu
University of California Berkeley USA,
Keywords: compact model, gate all around FETs, BSIM-CMG
Summary:FinFET is in mass production for its capability of scaling below 20nm. Thin silicon Fin surrounded by gate provides a superior channel electrostatics resulting in higher on current (Ion) and better subthreshold swing. The same thin body concept was also implemented in planar fully depleted silicon-on- insulator (FDSOI) transistors. Both solutions have a very thin body which has solved the problem of sub-surface leakages and poor gate control over the channel. In FinFET, the thin body is obtained by etching the silicon into thin fin shape. In every generation, semiconductor companies have made this fin thinner to have fin thickness (Tfin) nearly one-third of the gate lengths Lg. To achieve higher electrical width per device footprint, the fin height is increased in every generation. Below 5nm technology node, it may not be possible to make this fin any thinner and taller because of cleaning and etching issues during manufacturing. In such condition, gate-all-around (GAA) FET may become the preferred choice. Due to its gate all around structure, it offers better electrostatic control which enables continued CMOS device scaling. GAA structures may take different shapes. IRDS-2016 (ITRS 2.0) roadmap shows that vertically stacked nanowires (source at bottom and drain at top) will be suitable for logic applications at 5nm technology node and beyond. For the past several years, world’s leading fabrication companies are working on GAA FETs to meet IRDS prediction for advanced nodes. Samsung was the first who introduced multi-bridge-channel FET in 2003. Recently, IMEC has fabricated vertically stacked horizontal Si nanowire FET at scaled dimensions: 8nm diameter, 45nm lateral pitch, and 20-nm vertical separation. IBM has demonstrated horizontally stacked GAA nanosheet structure as replacement of FinFET at 5nm technology node and beyond. These devices show excellent subthreshold swing at a performance level comparable to FinFET devices. Thus, GAA is one of the most promising devices for future technology nodes. Hence it is important to have a compact model for such GAA structures. The BSIM-CMG is the first industry standard compact model for the common multigate FETs model which is developed to simulate double gate (DG), triple gate and gate-all-around (GAA) FinFETs. With this single model, we no longer have to deal with the radius of wire or thickness of fin. Instead, we have the term for a total charge as a function of insulator capacitance Cins, channel width Wch, channel doping Nch and channel cross-sectional area Ach. Therefore, this unified model can capture any cross section like nanosheet, nanowire, non-circular wire. This study shows that the BSIM-CMG unified multi-gate MOSFET model is ready for production design of silicon GAA based circuits and technology-product co-development for future technology nodes. In this work, we demonstrate model’s predictability for different shapes of gate-all-around (GAA) FETs and validated the model against the reported GAA FETs: stacked GAA nanosheet, stacked nanowire MOSFETs, Multi-bridge-channel MOSFETs, and Twin silicon nanowire MOSFETs.