Three Operation Modes of 6T-SRAM Using 5nm-Node Multi-Vt FD-SOI MOSFETs

J-Y. Chen, S-H. Chen, M-H. Chiang
National Cheng Kung University,

Keywords: CMOS, SRAM, FD-SOI


As CMOS technology continues to scale, many physical limitations mostly related to short channel effect (SCE) [1] [2] have surfaced. The fully depleted silicon-on-insulator (FD-SOI) MOSFET with excellent electrostatic control provides a good solution to reduce SCEs. We can control its threshold voltage (Vt) by modifying back bias or changing substrate doping [3]. The FD-SOI structure is shown in Fig. 1 with channel length = 11.6 nm, effect channel length = 9.3 nm, EOT = 0.6 nm, box thickness = 10 nm, and off-current (IOff) = 100 nA/μm at |VD| = 0.77 V. The body thickness (TBody) is referred to the ratio between LG and TBody in [4]. Figure 2 shows simulated IDS-VGS characteristics for both n- and p-channel FD-SOI MOSFETs. We can observe a good subthreshold swing and excellent DIBL (Table. 1). Figure 3 shows a Vt window of 107 mV by modifying its back bias from VDD to ground. Figure 4 demonstrates a Vt window of 129 mV by using different substrate doping levels at 0 V back bias. This work proposes an SRAM design methodology for various application requirements using the back bias technique. Figures 5 and 6 show extracted SNM and write current from butterfly curves and N-curves, respectively [5][6]. An analytical macro-model [7] is used to predict the 6T-SRAM cell performance. This work design the 6T-SRAM in three different modes: standard mode (SD), high-performance mode (HP) and low-voltage mode (LV). First, we adjust the gate work function to limit Ioff to 100 nA/um as the back biases (to source voltage (VBS)) are 0.77 V for n-FETs and -0.77 V for p- FETs. Further, we fix the back bias for both PU and PD transistors at VDD or ground and then adjust the back bias for PG transistors from ground to VDD. All combinations of the back bias in PD and PU substrate are listed in Table 2. The SNM and writeability results are shown in Fig. 7. In case 2 and case 3, PU and PD transistors on one side can share the same substrate due to the same back bias. Nevertheless, in case 1 and case 4, the substrates of PU and PD transistors are independent due to their different back biases. Therefore, even though we can get the best SNM in case 4 and the highest write current in case 1, we still suggest case 2 and case 3 for the latter designs owing to the use of smaller area for controlling circuitry. The SNM and IW of the three different modes of 6T-SRAM are summarized in Table 3. In HP mode, we increase the back bias to 0.77 V. In LV mode, we decrease the back bias to 0 V. In standard mode, we set the back bias to 0.4 V for PG and 0.77 V for PD and PU. In conclusion, the area efficient 6T-SRAM design technique using 5nm-node mutil-Vt FD-SOI devices has been demonstrated using the properly designed substrate-bias configuration.