Hierarchical Memory Modeling for Reliable Integration

Y. Cao, Z. Xu, C. Yang, K. Sutaria, C. Chakrabarti
Arizona State University, US

Keywords: memory devices, reliability modeling


This paper proposes a hierarchical modeling methodology for emerging memory devices. It starts from the generic behavioral model of a digital memory, the finite-state-machine (FSM). The FSM is then mapped to a common structural model, using an equivalent circuit for SPICE simulation. Furthermore, it integrates device-level models of various memory types, in order to comprehend the underlying physical mechanisms. Finally, this framework investigates leading reliability concerns, and develops external modules for them. These reliability modules include geometry change, material fluctuations, temporal shift, as well as variations in CMOS transistors that are used in the periphery circuitry for Read and Write operations. Such a generic modeling methodology is capable of path-finding at the early stage, evaluating the tradeoffs among different process/design choices, and adaptively developing reliable design solutions.