Measurement and Characterization of Interconnect Process Parameters for VLSI Design

N. Arora
Silterra, MY

Keywords: compact modeling, VLSI design


In this presentation we would discuss an innovative approach that has been tested for accurate measurement and characterization of interconnect process parameters required for VLSI chip design in sub-100nm process nodes, where process variations, gate oxide leakage and dielectric leakage of multi-conductor dielectric system are severe. It is shown that by making resistance R and capacitance C measurements on simple test structures fabricated through the process, one can easily find all interconnect related process parameters, including shape of the wires, by invoking field solver and non-linear optimization. This non-destructive interconnect electrical characterization method gives interconnect thickness, width and dielectric thickness which are in agreement with the most accurate but expensive and destructive SEM method. However, this characterization method does require accurate on-chip capacitance values. Here we also discuss the new methodology and implementation of measuring on-chip capacitance that avoids the use of reference circuitry required for the most commonly used indirect or on chip method such as Charge Based Capacitance Measurement (CBCM) method. This new method enables accurate measurement of both total and coupling capacitance of any two interconnects (wires or tracks) in the presence of any other wires down to aF range for sub-100 nm process nodes.