Modeling of Dynamic Threshold Voltage of High K Gate Stack and Application in FinFET Reliability

H. He, C. Ma, C. Wang, A. Zhang, J. He
Peking Univeristy, CN

Keywords: dynamic threshold voltage, nanoscale device, FinFET, reliaiblity modeling, circuit performance simulation


A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of Id is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.