Physics-based MIT Virtual Source Negative Capacitance FET model (MVSNC): Circuit-Performance Evaluation of NCFETs under Dielectric Leakage Scenarios

U. Radhakrishna
United States

Keywords: negative capacitance FET, FE-oxide, MVS


We present a circuit-level simulation study of negative capacitance field-effect transistors (NCFETs) incorporating the effects of dielectric (DE)-leakage in the presence of a floating intermediate metal gate. DE-leakage, however small, forces the FE-oxide initially in positive-capacitance state (PC-state) during transient device operation and affects the device performance in NCFET-based circuits. In this work, a physics-based compact model (MVSNC) is used as a tool to investigate the impact of DE-leakage on circuit-level transient performance along with design techniques such as work-function engineering (WFE) that can mitigate leakage effects. The MVSNC model is used to investigate the performance benefits of NCFET technology under different leakage scenarios by looking at the behavior of NCFET-inverters and ring oscillators (RO) constructed using baseline 45-nm generation MOSFETs. In each of the circuit-level evaluations, NCFET technology outperforms baseline MOSFET technology in terms of scalability of supply voltage and reduced total power consumption (static and dynamic powers) for the same speed of operation. This is true for both non-leaky and leaky DE scenarios, provided leakage-aware (LA)-design through WFE is adopted. We believe that these results and the simulation methodology will be insightful for designing NCFET-based circuits and studying the system level advantages of this technology.