Analytical Surface Potential Solution for Low Effective Mass Channel Common Double Gate MOSFET

A.S. Chakraborty, S. Jandhyala, S. Mahapatra
Indian Institute of Science, Bangalore,

Keywords: low effective mass, compact modeling, double gate MOSFET


Obtaining an accurate although computationally efficient analytic solution for surface potential is the key step towards developing compact model for Low Effective Mass channel material Common Double Gate (CDG) MOSFETs [1]. In our previous work [1], we have verbosely arrived at a completely physical surface potential (SP) model compatible for a wide range of effective masses, material thickness and gate-oxide asymmetry, developed without ever using an unphysical empirical fitting. The resultant SP model (equation (32) in [1]) can be obtained by equating f = 0 in equation (1) shown in Fig. 1. Although a direct approach of solving the SP would be using numerical iterations [1], this work proposes an efficient algorithm which solves the SP in a single iteration thereby increasing the speed in many-folds. The ingenuity lies in finding a smart initial guess , using sub-band wise asymptotes of (1). The flowchart in Fig. 2, and the adjoining plot describe simple 3-step algorithm. We have earlier developed efficient compact models for CDG MOSFETs drain current and terminal charges [2] under quantum drift-diffusion, also devoid of any fitting parameter, which we re-validated in this work (Fig. 3 and 4). Throughout we used charge neutrality condition QG + QD + QS=0, QG, QD, QS being the charge due to two gates and partitioned charge at drain and source respectively[2]. The effectiveness of the proposed algorithm is proven by comparing the analytical solution using the algorithm, with exact numerical solution of SP alongside data obtained from ATLAS [3]. We have further implemented a CMOS Inverter and a 15-stage Ring oscillator using the smart algorithm and compact models of surface potential, drain current and terminal charge ([1],[2]) in SmartSpice circuit simulator of SILVACO [4]. Another salient feature of this work is that we have shown the effect of quantum confinement (described in detail in [1]), in circuit level (Fig. (5) and (6) ). By limiting the maximum number of sub-bands in the model (nmax) within 1, 2 or 3 and thus playing with the the quantum confinement, we have shown how the DC characteristics of the CMOS inverter changes (Fig. (5)). As number of charge carriers reduce by reducing nmax, the amount of current through the MOSFET also drops resulting into increasing delay at the output and delayed switching. These are evidently described in Fig. 5 and 6. This work efficiently demonstrates the plausibility of the compact models ([1],[2]) for use in future circuital applications. REFERENCES [1] A. S. Chakraborty, S. Mahapatra, “Surface Potential Equation for Low Effective Mass Channel Common Double-Gate MOSFET”,IEEE Trans. Electron Devices, Vol. 64, No. 4, pp. 1519-1527, April 2017. [2] A. S. Chakraborty, S. Mahapatra, “Compact Model for Low Effective Mass Channel Common Double-Gate MOSFET”, under review in IEEE Trans. Electron Devices. [3] Users’ Manual of Silvaco ATLAS, version 5.20.2.R [Available] [4] Users’ Manual of Silvaco SmartSpice, version 4.10.6.R [Available]