A Predictive Resistive RAM Compact Model with Synaptic Behavior for Circuit Simulations

J.W. Lee, C.-H. Hsu, M.H. Chiang
National Cheng Kung University,

Keywords: RRAM, compact model


Artificial intelligence has come to its new era with the fast growth of machine learning algorithm. However, the conventional Von-Neumann architecture could consume excessive energy during the training process. At this moment, the memristor sheds a light on development of non-Von-Neumann architecture and provides semiconductor industry with a better solution for the optimization of certain learning algorithm [1]. Among many of the emerging memory technologies, Resistive Random Access Memory (RRAM) is regarded as one of the most promising candidates for next generation memory with its high density, fast switching speed, nonvolatile storage, low power consumption and its neuromorphic characteristic. Compared with other competitors, RRAM is more compatible with conventional CMOS fabrication environment and process [2]. Operation of RRAM usually contains of forming/set/reset. In the forming process, the conductive filament (CF) is generated in the dielectric layer of the Metal-Insulator-Metal structure of RRAM. Set and reset processes drive the memory to low resistant state (LRS) and high resistant state (HRS), respectively. Fig.1 shows the I-V characteristics of an RRAM cell with resistance state switching between HRS and LRS. The operation of RRAM could mimic the synaptic behavior, as shown in Fig. 2, in the human brain – combining the ability of memory and calculation. In order to bring the single RRAM device behavior and performance to higher system level, we provide a compact model of RRAM showing bipolar operation of programming/erase. With the physically based description of RRAM behavior, we could carry out the optimized prediction of timing and biasing in previous work [3]. The model is now extended to include the synaptic behavior. By applying repetitive pulse treatment (training), the LRS current of RRAM cell is improved (analogy to synapse conductance) (Fig. 3 and Fig. 4). This phenomenon may be caused by the expanded CF. Under a given bias, the chemical reaction between metal and dielectric layer creates oxygen vacancies and each of the successive pulse contributes to the formation of CF [4]. Fig. 5 shows the flow of modules in this work. Forming voltage module first determines the forming voltage. Current calculation module calculates the current in LRS and accounts for the transition in reset process. Memory module switches the memory state during each process. Training module calculates the number of successive pulses (positive or negative sweep) and clears the train effect if the state changes from HRS to LRS or vice versa. Temperature module calculates the thermal effect in RRAM cell. The model parameters could be simply calibrated and used in SPICE simulation for circuit level design. How to link the physical mechanism to the compact model is discussed in the paper. Design insight based on the synaptic plasticity is provided as well.