Carbon Nanotube Transistor Technology for the 5 nm Technology Node and Beyond

Q. Cao
IBM T.J. Watson Research Center,
United States

Keywords: carbon nanotube, transistor, CMOS

Summary:

Conventional scaling of Si complementary metal-oxide semiconductor (CMOS) devices provided ever-improved transistor performance, density, power, and cost in the last four decades. However, it has become very difficult in recent 10 years with Si devices approaching their physical limits. Here we will discuss the major difficulties in scaling beyond 5 nm technology node, and suggest carbon nanotubes as a very promising candidate to replace Si in high-performance logic transistors at 5 nm node and beyond. Compared to Si, nanotubes have atomically smooth intrinsic ultrathin body (~ 1 nm in diameter) which enables superior electrostatic control to minimize the off-state leakage current even at ultra-small device dimensions. In addition, nanotubes, due to quantum confinement, have carrier saturation velocity several times higher than silicon and III-V semiconductor, which enables faster switching at ballistic limit. I will introduce recent advances in building high performance nanotube transistors with extremely scaled device dimensions including both device channel length and contact length. Manufacturability challenges for make nanotube transistors become a practical device technology will then be discussed. Recent progresses in nanotube purification, nanotube assembly, and device engineering suggest these obstacles are surmountable. A concluding discussion highlights most significant challenges remained and provides perspectives on the future of carbon nanotube based nanoelectronics.