2014 Workshop on

Compact Modeling

WCM - Compact Modeling

WCM - Compact Modeling

Symposium Chair

Xing ZhouXing Zhou
Professor
Nanyang Technological University, Singapore

Confirmed Invited Speakers

Mansun ChanMansun Chan
Professor, Dept of Electronic & Computer Engineering
Hong Kong University of Science and Technology, Hong Kong
Yogesh ChauhanYogesh Chauhan
Assistant Professor, Department of Electrical Engineering
Indian Institute of Technology Kanpur, India
Binbin JieBinbin Jie
Professor, Department of Physics
Xiamen University, China
Chihtang (Chih-Tang) SahChihtang (Chih-Tang) Sah
Professor, Department of Physics
Xiamen University, China
Mark S. LundstromMark S. Lundstrom
Don and Carol Scifres Distinguished Professor of Electrical and Computer Engineering
Purdue University
Mitiko Miura-MattauschMitiko Miura-Mattausch
Professor leading Ultra-Small Devices Engineering Laboratory
Hiroshima University, Japan
Michael SchröterMichael Schröter
Chair for Electron Devices and Integrated Circuits
Technical University, Dresden, Germany
Michael ShurMichael Shur
Acting Director, Center for Integrated Electronics Co-Director, NSF I/UCRC \\
Rensselaer Polytechnic Institute
Yan WangYan Wang
Tsinghua University, China
Gert-Jan Smit
NXP, Netherlands

Synopsis

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:

Symposium Sessions

Monday June 16

8:30Compact Models for Future Devices
10:30Compact Model Platforms
1:30Compact Model Tutorial: Modeling MOSFETs – Ballistic to Diffusive
3:30Compact Model Tutorial: The Solid State Physics View of Liquid State Chemistry – Semiconductor Compact Modeling of Liquids (quasi-Protons for quasi-Electrons and quasi-Impuritons for quasi-Impuritrons)

Tuesday June 17

8:30Compact Modeling: UTBSOI/passive element models
10:30Compact Modeling: HEMT models
1:30Compact Modeling Tutorial: Modeling of Thin-Film Transistors Based on Poisson Equation
3:30Compact Model Tutorial: CNTFET Based HF Electronics - State of the Art and Future Prospects
4:30Compact Modeling Tutorial: Unification of MOS Compact Models with the Unified Regional Modeling Approach

Wednesday June 18

9:00Compact Modeling: Double-gate models
10:30Compact Modeling: Surrounding-gate models
1:30Compact Modeling: NBTI/reliability/noise models

Symposium Program

Monday June 16

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8:30Compact Models for Future DevicesPotomac 1
Session chair: Xing Zhou, Nanyang Technology University, SG (bio)
8:30Solid State Physics View of Liquid State Chemistry (invited presentation)
B. Jie, C. Sah, Xiamen University, CN (bio)
9:00Terahertz Compact SPICE model for Simulation of Plasmonic Field Effect Transistors (invited presentation)
M. Shur, T. Ytterdal, A. Gutin, Rensselaer Polytechnic Institute, US (bio)
9:30Trap-induced apparent linearity of CNTFETs (invited) (invited presentation)
M. Haferlach, M. Claus, M. Schröter, TU Dresden, DE (bio)
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10:30Compact Model PlatformsPotomac 1
Session chair: Bin Jie Binbin, Xiamen University, China (bio)
10:30The NEEDS Initiative: Connecting Materials and Devices to Circuits and Systems (invited presentation)
M. Lundstrom, Purdue University, US (bio)
11:00Developing a Common Compact Modeling Platform for Model Developers and Users (invited presentation)
L. Zhang, M. Chan, HKUST, HK (bio)
11:30RF-noise modeling in MOSFETs: excess noise, symmetry, and causality (invited presentation)
G.D.J. Smit, A.J. Scholten, R.M.T. Pijper, L.F. Tiemeijer, R. van der Toorn, D.B.M. Klaassen, P. Scheer, A. Juge, NXP Semiconductors, NL (bio)
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1:30Compact Model Tutorial: Modeling MOSFETs – Ballistic to DiffusivePotomac 1
Session chair: Mark Lundstrom, Purdue University, US (bio)
The research challenges for MOSFETs today are about scaling below 10 nm channel lengths where traditional, textbook MOSFET theory must be questioned. Using simple models that have been backed-up by rigorous quantum mechanical simulations, this tutorial will show that the essential physics of very small MOSFETs can be simply understood. We begin with a discussion of the ballistic MOSFET and then discuss how carrier scattering affects the performance. We will explain why silicon MOSFETs operate surprisingly close to the ballistic limit – in spite of a large amount of scattering - and show that III-V HEMTs operate essentially at the ballistic limit. The reason why traditional concepts such as mobility and saturation velocity continue to have relevance will be discussed, and new concepts, like “ballistic mobility” and “injection velocity” will be introduced. Although the approach used in this tutorial appears to be much different from traditional MOSFET theory, we will show that it is easily related to the traditional approach. Finally, the application of this model in the analysis of experimental data will be discussed.
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3:30Compact Model Tutorial: The Solid State Physics View of Liquid State Chemistry – Semiconductor Compact Modeling of Liquids (quasi-Protons for quasi-Electrons and quasi-Impuritons for quasi-Impuritrons)Potomac 1
Session chair: Bin Jie Binbin and Tom Sah Chihtang, Xiamen University, China

Tuesday June 17

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8:30Compact Modeling: UTBSOI/passive element modelsPotomac 1
Session chair: Gert-Jan Smit, NXP, The Netherlands (bio)
8:30Modeling of Short-Channel Effect for Ultra-Thin SOI MOSFET on Ultra-Thin BOX (invited presentation)
H. Miyamoto, Y. Fukunaga, H. Zenitani, K. Kikuchihara, H.J. Mattausch, M. Miura-Mattausch, Hiroshima University, JP (bio)
9:00BSIMIMG: Compact Model for UTBBSOI MOSFETs (invited presentation)
Y.S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J.P. Duarte, C. Hu, IIT Kanpur, IN (bio)
9:30Passive Elements Modeling in Microwave/Millimeter-wave application (invited presentation)
Y. Wang, J. Yao, J. Luo, Y. Tang, Tsinghua University, CN (bio)
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10:30Compact Modeling: HEMT modelsPotomac 1
Session chair: Mitiko Miura-Mattausch, Hiroshima University, Japan (bio)
10:30Compact Model Characteristics for Generic MIS-HEMTs (invited presentation)
X. Zhou, S.B. Chiah, B. Syamal, H.T. Zhou, A. Ajaykumar, X. Liu, Nanyang Technological University, SG (bio)
11:00Analysis of Breakdown Characteristics in Gate and Source Field-Plate AlGaN/GaN HEMTs
H. Onodera, H. Hanawa, K. Horio, Shibaura Institute of Technology, JP
11:20InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG
S. Khandelwal, J.P. Duarte, N. Paydavosi, Y.S. Chauhan, J.J. Gu, M. Si, P.D. Ye, C. Hu, University of California, Berkeley, US
11:40Modeling of AlGaN/GaN FinFET
C. Yadav, S Khandelwal, Y.S. Chauhan, Indian Institute of Technology Kanpur, India, IN
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1:30Compact Modeling Tutorial: Modeling of Thin-Film Transistors Based on Poisson EquationPotomac 1
Session chair: M. Miura-Mattausch (bio)
Bulk-MOSFETs are still the most successfully utilized integrated devices for real circuit applications. However, to achieve better circuit performances, thin-film transistors have been developed. Two such thin-film devices are the SOI-MOSFET and the double-gate MOSFET for better gate controllability. Additionally, the thin-film transistor concept has been extended from the conventional silicon crystalline material to amorphous and polycrystalline silicon and to different semiconductor materials including organic semiconductors. The focus of this tutorial is the compact modeling of the thin-film transistors for enabling the simulation of circuits utilizing these devices. A very important specific feature of advanced thin-film transistors is the fact that not only the front-gate control but also a back-gate control can occur at the same time. The basic physics of the thin-film transistors are included in the Poisson equation, which is the equation describing the relationship between the carrier density and the potential distribution within the device induced by the applied biases at the device terminals. How to solve the Poisson equation and how to derive analytical initial values for these solutions, to enable the compact modeling of thin-film transistors, is discussed.
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3:30Compact Model Tutorial: CNTFET Based HF Electronics - State of the Art and Future ProspectsPotomac 1
Session chair: M. Schroter (bio)
Introduction: Carbon nanotubes (CNTs) were the center of attention in the material science (i.e. physics and chemistry) community during the nineties and early 2000s. CNTs possess a number of advantageous properties which would make CNT field-effect transistors (FETs) for certain applications superior compared to conventional bulk semiconductors. In particular, the one-dimensional (1D) transport in CNTs can lead not only to a low scattering rate and high current carrying capability but also to a linear relation between drain current and input (gatesource) voltage. While THz performance has been predicted for ideal CNTFET structures, practically existing processing and materials related issues have limited the HF performance so far. Therefore, additional electrical features, which are unavailable in existing device technologies, and access to more advanced fabrication tools (such as 180nm lithography) are required for CNTFET technology to become competitive to advanced incumbent MOSFET and HBT technologies. This paper provides an overview on the state-of-the-art of CNTFET technology in terms of manufacturable fabrication, electrical device performance, device modeling, and circuit design from a practical engineering applications point of view. Device fabrication: Various existing approaches will be discussed with emphasis on manufacturability of CNTFETs and integrated circuits for RF applications. Furthermore, the selection of substrate and compatibility of CNTFET technology with incumbent technologies (e.g. CMOS) will be discussed. Finally, a brief overview will be given on novel and potentially useful methods for making the necessary improvements for fabricating devices with competitive performance. Device Modeling: Since CNTFETs are true nanoscale devices, a wide range of simulation tools have been utilized for analyzing their properties and performance, ranging from atomistic (ab-initio) methods over Schrödinger- and Boltzmann-Poisson solvers to compact models. Common to all existing numerical device simulation methods is their focus on just single-tube devices and their extremely long simulation times, which limits their suitability for device design. Similarly, almost all compact models focus on single-tube FETs and assume ideal structures. This paper will review the existing tools and their limitations as well as provide solutions for their improvement and extension to multi-tube multi-finger devices required for real-world (50Ω based) applications. A working compact model for analog RF applications will be presented. Electrical performance: The best fabricated CNTFETs have reached peak extrinsic operating frequencies (fT and fmax) of at least 10GHz. At first glance, this appears to be suitable for addressing the RF market below about 3GHz. The paper will discuss the electrical DC, AC, power and noise characteristics for state-of-the-art high-frequency CNTFET structures along with the still existing issues associated with the fabrication process and measurement issues resulting in apparent linearity. Also, the wide-spread confusion among the circuit design community resulting from literature and business news on multi-10 and even multi-100GHz CNT and graphene based FETs will be clarified. Circuits: Since CNTFET technology is still in an emerging state, only a few RF circuits have been designed so far. Their performance will be reviewed and the major limiting factors resulting from the device characteristics will be pointed out. In addition, the potential linearity of CNTFETs will be discussed and compared to other integrated technologies. Conclusion: The most important achievements of developing a practically useful CNTFET technology will be summarized, followed by a list of still existing obstacles for turning CNTFETs into a competitive technology. Finally, the prospects of a (more) mature CNTFET technology will be discussed.
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4:30Compact Modeling Tutorial: Unification of MOS Compact Models with the Unified Regional Modeling ApproachPotomac 1
Session chair: Xing Zhou, Nanyang Technology University, SG (bio)
History has witnessed generations of compact models that are used for designing VLSI circuits as the CMOS technology scales over the past decades. As conventional planar bulk and silicon-on-insulator (SOI) technologies continue to scale into the 22nm technology node and below, CMOS-compatible devices such as multigate (MG) FinFETs and nanowire MOSFETs as well as III-V channel metal-insulator-semiconductor (MIS) high electron-mobility transistors (HEMTs) are emerging as future generation device building blocks. In this tutorial, we review the history and current trends in MOSFET compact modeling, and challenges in extending bulk/SOI models to emerging MG-FinFETs and MIS-HEMTs in a unified approach. A unified regional modeling (URM) approach is introduced for unification of FET compact models, encompassing bulk, partially/dynamically/fully-depleted SOI, double-gate (DG) and gate-all-around (GAA) MOSFETs, and generic MIS-HEMTs, which are scalable over the entire range of gate length/width as well as body doping and thickness. Other challenges in modeling higher-order effects are discussed, such as short-channel with quasi-2D solution, model symmetry and asymmetric source/drain (S/D), dopant-segregated Schottky-barrier (SB) S/D with ambipolar transport, poly-depletion/accumulation, quantum-mechanical, floating-body, 2-dimensional electron gas (2DEG), velocity-saturation and quasi-ballistic effects. Major bench-mark tests of the model (Xsim) in comparison with numerical TCAD and available measurement data are presented.

Wednesday June 18

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9:00Compact Modeling: Double-gate modelsPotomac 1
Session chair: Yogesh Chauhan, Indian Institute of Technology Kanpur, India (bio)
9:00Drain Current Model for Thin Body Undoped and Lightly Doped Double-Gate MOSFETs
H. Abd Elhamid, B. Ineguez, Y. Ismail, MJ. Deen, Zewail City of Science and Technology, EG
9:20NQS Modeling of independent DG MOSFET using RTA Approach
N. Sharan, S. Mahapatra, Indian Institute of Science, IN
9:40A Threshold Voltage Modeling for a Spacer Trapping Memory Cell Using Verilog-A
H. Shrimali, V. Liberali, Università degli Studi di Milano, IT
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10:30Compact Modeling: Surrounding-gate modelsPotomac 1
Session chair: Michael Schröter, Technical University Dresden, Germany (bio)
10:30A Physics Based Potential Model for Cylindrical Surrounding Gate MOSFETs with SiO2- Core Si-Shell Structure
X. Zhang, J. He, M. Chan, C. Du, Y. Ye, W. Zhao, W. Wu, W. Wang, PKU-HKUST ShenZhen-HongKong Institution, CN
10:50Analytic Compact Model of Ballistic and Quasi-ballistic Cylindrical Gate-All-Around MOSFET Incorporating Drain-Induced Barrier Lowering Effect
H. Cheng, S. Uno, K. Nakazato, graduate school of engineering, Nagoya University, JP
11:10An Analytic Potential Based Model for Gate-All-Around Nanowire Tunnel-FETs
Y. Liu, J. He, M. Chan, Peking University Shenzhen SOC Key Laboratory, CN
11:30Simulation Study on Dopant Fluctuation Impact on SRG MOSFET Device and Circuit Performane
H. Wang, J. He, Y. Liu, Peking University Shenzhen SOC Key Laboratory, CN
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1:30Compact Modeling: NBTI/reliability/noise modelsPotomac 1
Session chair: Xing Zhou, Nanyang Technology University, SG (bio)
1:30Silicon Nanowire Metal-Oxide-Semiconductor Field Effect Transistor NBTI Effect Modeling and Application in Circuit Performance Simulation
C. Ma, J. He, M. Chan, C. Du, Q. He, Y. Ye, W. Zhao, W. Wu, X. Zhang, W. Wang, PKU-HKUST ShenZhen-HongKong Institution, CN
1:50Compact Negative Bias Temperature Instability Model for Nanoscale FinFET Reliability Simulation
C. Zhang, W. Wang, Y. Liu, Y. Ye, W. Zhao, J. He, W. Wu, Peking University Shenzhen SOC Key Laboratory, CN
2:10Effects of sub-threshold operation on 32 nm technology node PMOSFETs evaluated from the perspective of two-stage NBTI model
H. Hussin, N. Soin, M.F. Bukhori, Universiti Teknologi MARA, MY
2:30Investigation on Impact of Different Defects based on Different Trap Energy Level in the Framework of Two-Stage NBTI model
H. Hussin, N. Soin, M.F. Bukhori, Universiti Teknologi MARA, MY
2:50Noise Modeling in BSIM6 Compact Model
H. Agarwal, S. Khandelwal, Y.S. Chauhan, C. Hu, Indian Institute of Technology Kanpur, India, IN
Intrinsic Models
  • Bulk MOSFET
  • SOI MOSFET (partial-/full-depletion)
  • Multiple-Gate FET (DG/TG/GAA)
  • High-Voltage/LDMOS
  • Thin-Film Transistor (TFT)
  • Schottky-Barrier/Tunneling FET (SB-FET/TFET)
  • Bipolar/Junction (BJT/HBT/SiGe/JFET)
  • HEMT (GaN/InGaP/InGaAs)
  • RF/noise
Extrinsic/Interconnect Models
  • Parasitic elements
  • Passive device
  • Diode
  • Resistor
  • ESD
  • Interconnect
Atomic/Quantum Models
  • Ballistic device
  • Carbon-Nanotube (CNFET)
  • Organic FET
Statistical Models
  • Statistical/variability
  • Reliability/hot carrier
  • Numerical/TCAD/table-based
Multi-Level Models
  • Subcircuit model
  • Gate/block model
  • Behavioral model
Model Extraction and Interface
  • Parameter extraction and optimization
  • Model-simulator interface
  • Model standardization

Workshop Program
WCM2014 Program will be posted at the Nanotech website. http://www.techconnectworld.com/Nanotech2014/sym/WCM_Compact_Modeling.html

Tutorials
The following tutorials are planned:

  • Nanotransistors from a virtual source perspective
    Mark Lundstrom, Purdue University, USA
  • Thin film transistors
    Mitiko Miura-Mattausch, Hiroshima University, Japan
  • CNTFET based HF electronics - State of the art and future prospects
    Michael Schröter, University of Technology Dresden, Germany
Presentation Slides: Contributed presentation slides will be posted after the conference.

Websites for Proceedings: Workshop proceedings will be available online after the conference.

12th WCM2014 websites: http://www.techconnectworld.com/Nanotech2014/sym/WCM_Compact_Modeling.html
11th WCM2012 website: View 2012 WCM program and presentation slides
10th WCM2011 website:
View 2011 WCM program and presentation slides
 9th WCM2010 website: View 2010 WCM program and presentation slides
 8th WCM2009 website:
View 2009 WCM program and presentation slides
 7th WCM2008 website:
View 2008 WCM program and presentation slides
 6th WCM2007 website:
View 2007 WCM program and presentation slides
 5th WCM2006 website: View 2006 WCM program and presentation slides
 4th WCM2005 website: View 2005 WCM program and presentation slides
 3rd WCM2004 website:
View 2004 WCM program and presentation slides
 2nd WCM2003 website: View 2003 WCM program and presentation slides
 1st WCM2002 website: View 2002 WCM program and presentation slides

Topics & Application Areas

  • Intrinsic Models: Bulk MOSFET
  • Intrinsic Models: SOI MOSFET (partial-/full-depletion)
  • Intrinsic Models: Multiple-Gate FET (DG/TG/GAA)
  • Intrinsic Models: High-Voltage/LDMOS
  • Intrinsic Models: Thin-Film Transistor (TFT)
  • Intrinsic Models: Schottky-Barrier/Tunneling FET (SB-FET/TFET)
  • Intrinsic Models: Bipolar/Junction (BJT/HBT/SiGe/JFET)
  • Intrinsic Models: HEMT (GaN/InGaP/InGaAs)
  • Intrinsic Models: RF/noise
  • Extrinsic/Interconnect Models: Parasitic elements
  • Extrinsic/Interconnect Models: Passive device
  • Extrinsic/Interconnect Models: Diode
  • Extrinsic/Interconnect Models: Resistor
  • Extrinsic/Interconnect Models: ESD
  • Extrinsic/Interconnect Models: Interconnect
  • Atomic/Quantum Models: Ballistic device
  • Atomic/Quantum Models: Carbon-Nanotube (CNFET)
  • Atomic/Quantum Models: Organic FET
  • Statistical Models: Statistical/variability
  • Statistical Models: Reliability/hot carrier
  • Statistical Models: Numerical/TCAD/table-based
  • Multi-Level Models: Subcircuit model
  • Multi-Level Models: Gate/block model
  • Multi-Level Models: Behavioral model
  • Model Extraction & Interface: Parameter extraction & optimization
  • Model Extraction & Interface: Model-simulator interface
  • Model Extraction & Interface: Model standardization
  • Other

Journal Submissions

Microelectronics Journal

Microelectronics Journal

Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on microelectronics.

For consideration into the Microelectronics Journal please select the “Submit to Microelectronics Journal” button during the on-line submission procedure.

Sensors & Transducers

On-line Journal ‘Sensors & Transducers’

Selected proceedings papers in the Electronics and Microsystems Track (MEMS & NEMS, Sensors & Systems, Micro & Nano Fluidics symposia, and MSM conference) will be reviewed and invited into a Special Issue of the on-line journal ‘Sensors & Transducers’.

For consideration into this Special Issue of the on-line journal ‘Sensors & Transducers’, please select the “Submit to Sensors & Transducers” button during the on-line submission procedure.

 

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