Modeling & Simulation of Microsystems

Modeling & Simulation of Microsystems

Symposium Sessions

Monday June 16

8:30Compact Models for Future Devices
10:30Compact Model Platforms
1:30Compact Model Tutorial: Modeling MOSFETs – Ballistic to Diffusive
3:30Compact Model Tutorial: The Solid State Physics View of Liquid State Chemistry – Semiconductor Compact Modeling of Liquids (quasi-Protons for quasi-Electrons and quasi-Impuritons for quasi-Impuritrons)

Tuesday June 17

10:30Modeling, Simulation and Informatics Town Hall Meeting
10:30Compact Modeling: HEMT models
1:30Compact Modeling Tutorial: Modeling of Thin-Film Transistors Based on Poisson Equation
Modeling & Simulation of Microsystems - Posters 1:30
3:30Compact Model Tutorial: CNTFET Based HF Electronics - State of the Art and Future Prospects
4:30Compact Modeling Tutorial: Unification of MOS Compact Models with the Unified Regional Modeling Approach

Wednesday June 18

9:00Compact Modeling: Double-gate models
10:30Compact Modeling: Surrounding-gate models
1:30Compact Modeling: NBTI/reliability/noise models

Symposium Program

Monday June 16

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8:30Compact Models for Future DevicesPotomac 1
Session chair: Xing Zhou, Nanyang Technology University, SG (bio)
8:30Solid State Physics View of Liquid State Chemistry (invited presentation)
B. Jie, C. Sah, Xiamen University, CN (bio)
9:00Terahertz Compact SPICE model for Simulation of Plasmonic Field Effect Transistors (invited presentation)
M. Shur, T. Ytterdal, A. Gutin, Rensselaer Polytechnic Institute, US (bio)
9:30Trap-induced apparent linearity of CNTFETs (invited) (invited presentation)
M. Haferlach, M. Claus, M. Schröter, TU Dresden, DE (bio)
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10:30Compact Model PlatformsPotomac 1
Session chair: Bin Jie Binbin, Xiamen University, China (bio)
10:30The NEEDS Initiative: Connecting Materials and Devices to Circuits and Systems (invited presentation)
M. Lundstrom, Purdue University, US (bio)
11:00Developing a Common Compact Modeling Platform for Model Developers and Users (invited presentation)
L. Zhang, M. Chan, HKUST, HK (bio)
11:30RF-noise modeling in MOSFETs: excess noise, symmetry, and causality (invited presentation)
G.D.J. Smit, A.J. Scholten, R.M.T. Pijper, L.F. Tiemeijer, R. van der Toorn, D.B.M. Klaassen, P. Scheer, A. Juge, NXP Semiconductors, NL (bio)
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1:30Compact Model Tutorial: Modeling MOSFETs – Ballistic to DiffusivePotomac 1
Session chair: Mark Lundstrom, Purdue University, US (bio)
The research challenges for MOSFETs today are about scaling below 10 nm channel lengths where traditional, textbook MOSFET theory must be questioned. Using simple models that have been backed-up by rigorous quantum mechanical simulations, this tutorial will show that the essential physics of very small MOSFETs can be simply understood. We begin with a discussion of the ballistic MOSFET and then discuss how carrier scattering affects the performance. We will explain why silicon MOSFETs operate surprisingly close to the ballistic limit – in spite of a large amount of scattering - and show that III-V HEMTs operate essentially at the ballistic limit. The reason why traditional concepts such as mobility and saturation velocity continue to have relevance will be discussed, and new concepts, like “ballistic mobility” and “injection velocity” will be introduced. Although the approach used in this tutorial appears to be much different from traditional MOSFET theory, we will show that it is easily related to the traditional approach. Finally, the application of this model in the analysis of experimental data will be discussed.
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3:30Compact Model Tutorial: The Solid State Physics View of Liquid State Chemistry – Semiconductor Compact Modeling of Liquids (quasi-Protons for quasi-Electrons and quasi-Impuritons for quasi-Impuritrons)Potomac 1
Session chair: Bin Jie Binbin and Tom Sah Chihtang, Xiamen University, China

Tuesday June 17

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10:30Modeling, Simulation and Informatics Town Hall MeetingCamelia
Session chair: Carlos Gonzalez, NIST; Stephanie Morris, NCI Office of Cancer Nanotechnology Research (bio)
-Enabling National Leadership in Sustainable Design
L. Friedersdorf, National Nanotechnology Coordination Office, US
-C. Gonzalez, National Institute of Standards and Technology, US
-S. Morris, National Cancer Institute, US
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10:30Compact Modeling: HEMT modelsPotomac 1
Session chair: Mitiko Miura-Mattausch, Hiroshima University, Japan (bio)
10:30Compact Model Characteristics for Generic MIS-HEMTs (invited presentation)
X. Zhou, S.B. Chiah, B. Syamal, H.T. Zhou, A. Ajaykumar, X. Liu, Nanyang Technological University, SG (bio)
11:00Analysis of Breakdown Characteristics in Gate and Source Field-Plate AlGaN/GaN HEMTs
H. Onodera, H. Hanawa, K. Horio, Shibaura Institute of Technology, JP
11:20InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG
S. Khandelwal, J.P. Duarte, N. Paydavosi, Y.S. Chauhan, J.J. Gu, M. Si, P.D. Ye, C. Hu, University of California, Berkeley, US
11:40Modeling of AlGaN/GaN FinFET
C. Yadav, S Khandelwal, Y.S. Chauhan, Indian Institute of Technology Kanpur, India, IN
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1:30Compact Modeling Tutorial: Modeling of Thin-Film Transistors Based on Poisson EquationPotomac 1
Session chair: M. Miura-Mattausch (bio)
Bulk-MOSFETs are still the most successfully utilized integrated devices for real circuit applications. However, to achieve better circuit performances, thin-film transistors have been developed. Two such thin-film devices are the SOI-MOSFET and the double-gate MOSFET for better gate controllability. Additionally, the thin-film transistor concept has been extended from the conventional silicon crystalline material to amorphous and polycrystalline silicon and to different semiconductor materials including organic semiconductors. The focus of this tutorial is the compact modeling of the thin-film transistors for enabling the simulation of circuits utilizing these devices. A very important specific feature of advanced thin-film transistors is the fact that not only the front-gate control but also a back-gate control can occur at the same time. The basic physics of the thin-film transistors are included in the Poisson equation, which is the equation describing the relationship between the carrier density and the potential distribution within the device induced by the applied biases at the device terminals. How to solve the Poisson equation and how to derive analytical initial values for these solutions, to enable the compact modeling of thin-film transistors, is discussed.
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Modeling & Simulation of Microsystems - Posters 1:30Expo Hall C
-A Computational Study on Detection of Ultra Small Volumes of Liquid and Solid Media in Microcavities Using Surface Acoustic Wave Devices
S.U. Senveli, O. Tigli, University of Miami, US
-Simple and Accurate Formula for the Electrostatically Actuated Curled Beam Problem
M. Younis, SUNY Binghamton, US
-Transmit and Receive of a cMUT Cell: Modeling and Experiments
S.P. Mao, X. Rottenberg, V. Rochus, P. Helin, A. Verbist, S. Severi, B. Nauwelaers, H.A.C. Tilmans, IMEC, BE
-TCAD Thermal Analysis of Gate Workfunction Engineered Recessed Channel MOSFET
G. Arora, M. Monika, R. Chaujar, Delhi Technological University, IN
-Impact of Parametric Variations on Heat Conductivity of Gate Electrode Work Function Engineered Recessed Channel MOSFET
M. Monika, G. Arora, R. Chaujar, Delhi Technological University, IN
-Thermal Behavior of Novel Transparent Gate Recessed Channel (TGRC) MOSFET: TCAD Analysis
A. Kumara, R. Chaujarb, M. Monikac, Delhi Technological University, IN
-Resonance Induced by a Time Varying Electric Field
J. Nimmo, I. Filikhin, B. Vlahovic, North Carolina Central University, US
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3:30Compact Model Tutorial: CNTFET Based HF Electronics - State of the Art and Future ProspectsPotomac 1
Session chair: M. Schroter (bio)
Introduction: Carbon nanotubes (CNTs) were the center of attention in the material science (i.e. physics and chemistry) community during the nineties and early 2000s. CNTs possess a number of advantageous properties which would make CNT field-effect transistors (FETs) for certain applications superior compared to conventional bulk semiconductors. In particular, the one-dimensional (1D) transport in CNTs can lead not only to a low scattering rate and high current carrying capability but also to a linear relation between drain current and input (gatesource) voltage. While THz performance has been predicted for ideal CNTFET structures, practically existing processing and materials related issues have limited the HF performance so far. Therefore, additional electrical features, which are unavailable in existing device technologies, and access to more advanced fabrication tools (such as 180nm lithography) are required for CNTFET technology to become competitive to advanced incumbent MOSFET and HBT technologies. This paper provides an overview on the state-of-the-art of CNTFET technology in terms of manufacturable fabrication, electrical device performance, device modeling, and circuit design from a practical engineering applications point of view. Device fabrication: Various existing approaches will be discussed with emphasis on manufacturability of CNTFETs and integrated circuits for RF applications. Furthermore, the selection of substrate and compatibility of CNTFET technology with incumbent technologies (e.g. CMOS) will be discussed. Finally, a brief overview will be given on novel and potentially useful methods for making the necessary improvements for fabricating devices with competitive performance. Device Modeling: Since CNTFETs are true nanoscale devices, a wide range of simulation tools have been utilized for analyzing their properties and performance, ranging from atomistic (ab-initio) methods over Schrödinger- and Boltzmann-Poisson solvers to compact models. Common to all existing numerical device simulation methods is their focus on just single-tube devices and their extremely long simulation times, which limits their suitability for device design. Similarly, almost all compact models focus on single-tube FETs and assume ideal structures. This paper will review the existing tools and their limitations as well as provide solutions for their improvement and extension to multi-tube multi-finger devices required for real-world (50Ω based) applications. A working compact model for analog RF applications will be presented. Electrical performance: The best fabricated CNTFETs have reached peak extrinsic operating frequencies (fT and fmax) of at least 10GHz. At first glance, this appears to be suitable for addressing the RF market below about 3GHz. The paper will discuss the electrical DC, AC, power and noise characteristics for state-of-the-art high-frequency CNTFET structures along with the still existing issues associated with the fabrication process and measurement issues resulting in apparent linearity. Also, the wide-spread confusion among the circuit design community resulting from literature and business news on multi-10 and even multi-100GHz CNT and graphene based FETs will be clarified. Circuits: Since CNTFET technology is still in an emerging state, only a few RF circuits have been designed so far. Their performance will be reviewed and the major limiting factors resulting from the device characteristics will be pointed out. In addition, the potential linearity of CNTFETs will be discussed and compared to other integrated technologies. Conclusion: The most important achievements of developing a practically useful CNTFET technology will be summarized, followed by a list of still existing obstacles for turning CNTFETs into a competitive technology. Finally, the prospects of a (more) mature CNTFET technology will be discussed.
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4:30Compact Modeling Tutorial: Unification of MOS Compact Models with the Unified Regional Modeling ApproachPotomac 1
Session chair: Xing Zhou, Nanyang Technology University, SG (bio)
History has witnessed generations of compact models that are used for designing VLSI circuits as the CMOS technology scales over the past decades. As conventional planar bulk and silicon-on-insulator (SOI) technologies continue to scale into the 22nm technology node and below, CMOS-compatible devices such as multigate (MG) FinFETs and nanowire MOSFETs as well as III-V channel metal-insulator-semiconductor (MIS) high electron-mobility transistors (HEMTs) are emerging as future generation device building blocks. In this tutorial, we review the history and current trends in MOSFET compact modeling, and challenges in extending bulk/SOI models to emerging MG-FinFETs and MIS-HEMTs in a unified approach. A unified regional modeling (URM) approach is introduced for unification of FET compact models, encompassing bulk, partially/dynamically/fully-depleted SOI, double-gate (DG) and gate-all-around (GAA) MOSFETs, and generic MIS-HEMTs, which are scalable over the entire range of gate length/width as well as body doping and thickness. Other challenges in modeling higher-order effects are discussed, such as short-channel with quasi-2D solution, model symmetry and asymmetric source/drain (S/D), dopant-segregated Schottky-barrier (SB) S/D with ambipolar transport, poly-depletion/accumulation, quantum-mechanical, floating-body, 2-dimensional electron gas (2DEG), velocity-saturation and quasi-ballistic effects. Major bench-mark tests of the model (Xsim) in comparison with numerical TCAD and available measurement data are presented.

Wednesday June 18

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9:00Compact Modeling: Double-gate modelsPotomac 1
Session chair: Yogesh Chauhan, Indian Institute of Technology Kanpur, India (bio)
9:00Drain Current Model for Thin Body Undoped and Lightly Doped Double-Gate MOSFETs
H. Abd Elhamid, B. Ineguez, Y. Ismail, MJ. Deen, Zewail City of Science and Technology, EG
9:20NQS Modeling of independent DG MOSFET using RTA Approach
N. Sharan, S. Mahapatra, Indian Institute of Science, IN
9:40A Threshold Voltage Modeling for a Spacer Trapping Memory Cell Using Verilog-A
H. Shrimali, V. Liberali, Università degli Studi di Milano, IT
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10:30Compact Modeling: Surrounding-gate modelsPotomac 1
Session chair: Michael Schröter, Technical University Dresden, Germany (bio)
10:30A Physics Based Potential Model for Cylindrical Surrounding Gate MOSFETs with SiO2- Core Si-Shell Structure
X. Zhang, J. He, M. Chan, C. Du, Y. Ye, W. Zhao, W. Wu, W. Wang, PKU-HKUST ShenZhen-HongKong Institution, CN
10:50Analytic Compact Model of Ballistic and Quasi-ballistic Cylindrical Gate-All-Around MOSFET Incorporating Drain-Induced Barrier Lowering Effect
H. Cheng, S. Uno, K. Nakazato, graduate school of engineering, Nagoya University, JP
11:10An Analytic Potential Based Model for Gate-All-Around Nanowire Tunnel-FETs
Y. Liu, J. He, M. Chan, Peking University Shenzhen SOC Key Laboratory, CN
11:30Simulation Study on Dopant Fluctuation Impact on SRG MOSFET Device and Circuit Performane
H. Wang, J. He, Y. Liu, Peking University Shenzhen SOC Key Laboratory, CN
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1:30Compact Modeling: NBTI/reliability/noise modelsPotomac 1
Session chair: Xing Zhou, Nanyang Technology University, SG (bio)
1:30Silicon Nanowire Metal-Oxide-Semiconductor Field Effect Transistor NBTI Effect Modeling and Application in Circuit Performance Simulation
C. Ma, J. He, M. Chan, C. Du, Q. He, Y. Ye, W. Zhao, W. Wu, X. Zhang, W. Wang, PKU-HKUST ShenZhen-HongKong Institution, CN
1:50Compact Negative Bias Temperature Instability Model for Nanoscale FinFET Reliability Simulation
C. Zhang, W. Wang, Y. Liu, Y. Ye, W. Zhao, J. He, W. Wu, Peking University Shenzhen SOC Key Laboratory, CN
2:10Effects of sub-threshold operation on 32 nm technology node PMOSFETs evaluated from the perspective of two-stage NBTI model
H. Hussin, N. Soin, M.F. Bukhori, Universiti Teknologi MARA, MY
2:30Investigation on Impact of Different Defects based on Different Trap Energy Level in the Framework of Two-Stage NBTI model
H. Hussin, N. Soin, M.F. Bukhori, Universiti Teknologi MARA, MY
2:50Noise Modeling in BSIM6 Compact Model
H. Agarwal, S. Khandelwal, Y.S. Chauhan, C. Hu, Indian Institute of Technology Kanpur, India, IN

In an effort to dramatically shorten development time and reduce prototyping costs, simulation activities have experienced phenomenal growth, generating a large number of point solutions, as well as integrated tools. The goal of this symposium is to bring together researchers, designers, programmers and vendors involved in microsystem developments. The event provides a forum for microsystem simulation specialists, allowing them to be exposed to the state of the art modeling techniques currently implemented in academic or industrial research, encouraging a free exchange of ideas and generating synergies between adjacent specialties.

Topics & Application Areas

  • Novel Computational & Numerical Methods
  • MEMS Device Modeling
  • Process Modeling
  • Device & Circuit Simulation
  • System & Optimization
  • Fluidic Device Simulation
  • Industrial case studies
  • Other

Sponsor & Exhibitor Opportunities

√ Nanotech Conference & Expo  

√ Microtech Conference & Expo  

√ Cleantech Conference & Expo  

*Sponsorship Opportunities: Contact Chris Erb

Platinum Sponsors

Lockheed Martin
Nanocomp Technologies

Association Sponsor

Clean Technology and Sustainable Industries Organization (CTSI)

Producing Sponsors

Nano Science and Technology Institute


TechConnect Acceleration Partners:

Aerojet Rocketddyne
General Atomics Electromagnetics
Harris Harris Group
Ingersoll Rand
Lockheed Martin
Sherwin Williams
Union Honest Investments
*Sponsorship Opportunities: Contact Chris Erb

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