A Threshold Voltage Modeling for a Spacer Trapping Memory Cell Using Verilog-A

H. Shrimali, V. Liberali
Università degli Studi di Milano, IT

Keywords: EEPROM memory characteristics simulation, FN current parameters, MOS capacitance characteristics, non-volatile memory, tunneling, behavioral model, hardware descriptive language


The threshold voltage of the flash memories varies with respect to the applied voltages at the respective terminal of a memory cell. This paper presents the modeling of the threshold voltage variation for an embedded spacer-trapping memory cell i.e. sidewall flash (S-Flash) memory. The effects such as velocity saturation of the transistor and the Fowler-Nordheim tunneling have been incorporated in the model. The proposed memory model has been simulated for the memory cell designed in a standard 0.18 um CMOS technology. The output results of the proposed model using Verilog-A show 94.9 ms of erasing time and the programing time of 33.4 ms, for the speed of 10 kHz. An increment of 930 mV of the threshold voltage during the programming mode has been recorded.