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Hardware accelerated interconnect capacitance extractor for VLSI design (invited presentation)

N. Arora
Silterra Malaysia Sdn. Bhd., US

Keywords: interconenct capacitance, parasitic extraction, Monet Carlo method, hardware acceleration

Abstract:

The downscaling of integrated circuit (IC) devices toward nanometer dimensions has resulted in increase in process variability due to IC manufacturing effects and in addition wires are packed closely together leading to increases in undesirable coupling effects, crosstalk, and noise etc. Conventional full chip parasitic extractors (tools) use a predefined library of cells with capacitance models generated for each technology (process) node. All model-based extractors thus always will generate errors when the exact shape of the cell (pattern) is not in the library (incorrect pattern matching), or when the silicon wire thickness/width is different than assumed, resulting in loss of circuit performance and yield. This paper describes a fast and accurate, Design-for-Manufacturing (DFM) aware, Monte-Carlo (MC) based algorithm that can be used for accurate capacitance calculation of IC chips. Using off-the-shelf Graphical Processor Units (GPU) board plugged into a PC the speed of capacitance (C) calculation of wires in nanoscale IC could easily be increased by a factor of 100X or more Due to the speed of extraction it is now possible to do full chip capacitance extraction making direct use of the field solver on full chip thus getting most accurate capacitance values in an IC chip. Advantage of this direct solver based approach over the conventional model based approach has been discussed. It is shown that using 2 GPU and Intel Xenon processor at 2GHz we can run design of 1M nets in few hours.
 
 
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