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Simulation of Field-Plate Effects on Surface-State-Related Lag and Current Slump in GaAs FETs

T. Tanaka, K. Itagaki, A. Nakajima, K. Horio
Shibaura Institute of Technology, JP

Keywords: GaAs FET, power slump, drain lag, gate lag, surface state


In this study, we carry out two-dimensional transient analysis of field-plate GaAs MESFETs by taking surface states into account. Quasi-pulsed current-voltage curves are derived from the transient characteristics. We show that drain lag and current slump (power slump) due to surface states are reduced by introducing a field plate because the fixed potential at the field plate mitigates trapping effects of the surface states. The dependence of lag and current slump on the field-plate length and SiO2 passivation layer thickness is also studied. We show that it is possible to reduce the current slump and maintain the high-frequency performance of GaAs FETs at optimum values of the field-plate length and SiO2 layer thickness.
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