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Process Variability Modeling for VLSI Circuit Simulation (invited presentation)

S.K. Saha
SuVolta, Inc., US

Keywords: process variability, statistical compact modeling, intradie variability, interdie variability


It is well known that the process variability has severely impacted the delay and power variability in VLSI devices, circuits, and chips, and the impact of process variability keeps increasing as MOSFET devices and CMOS technologies continually scale down. The increasing amount of intra-die variability in scaled devices has imposed an enormous challenge on conventional VLSI design methodologies. Due to variability constraints, a circuit optimized using such methodologies is more susceptible to random performance variation. Therefore, to mitigate the risk of process variability, statistical methodologies have become indispensable for modern VLSI circuit design. And, to enable statistical VLSI circuit design, suitable methodologies must be used to generate statistical compact model for circuit simulation. Though the variability modeling has been widely reported, however, the systematic methodologies to generate statistical models for circuit simulation have not yet been reported. This presentation discusses methodologies to generating statistical compact models for VLSI circuit analysis.
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