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Wafer level packaging solutions for hermetic sealing, temperature control and vibration isolation (invited presentation)

J. Mitchell, S. Lee, K. Najafi
ePack, Inc., US

Keywords: MEMS

Abstract:

This talk will focus on challenges in applying cost effective and performance enhancing MEMS wafer-level packaging technologies. Although MEMS technology is based on integrated circuit (IC) technology, the MEMS market ($8B) has lagged behind the IC market (>$250B). The difficulty in developing packaging for MEMS devices has been one of the main factors causing this slower growth. In fact, packaging generally accounts for 50 - 80% without cost saving/scalable wafer-level packaging. ePack is currently working to apply 2 different wafer level packaging technologies. The first are wafer level capping (WLC) processes which include the use of low temperature solders (200 -400 ÂșC) and in some cases vertical feedthrough (VFT) electrical interconnects. WLC allows for cost effective hermetic (or vacuum) sealing of thousands of devices at a time on a wafer and is appropriate for high volume consumer applications. The second technology is the environmental resistant package (ERP). This technology involves hybrid assembly and vacuum encapsulation of high performance MEMS devices onto an isolation platform which allows for low power (10-50 mW) oven control and a mechanical filter which attenuates high frequency vibration. For the ERP we are targeting 99% attenuation at the natural frequency of the resonant device.
 
 
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