Industry-Government-University Partnerships on Research towards Nanoelectronics

Bob Doering

Bob Doering

Senior Fellow and Research Manager

Texas Instruments

Dr. Doering is a Senior Fellow and Research Manager at Texas Instruments. He is also a member of TI’s Technical Advisory Board, Kilby Labs Review Board, External Development and Manufacturing Leadership Team, and Executive University Research Steering Team. His previous positions at TI include: Manager of CMOS and DRAM Process Development, Director of the Microelectronics Manufacturing Science and Technology (MMST) Program, Director of Scaled-Technology Integration, Manager of Future-Factory Strategy, and Manager of Technology Strategy.

He received a B.S. degree in physics from the Massachusetts Institute of Technology in 1968 and a Ph.D. in physics from Michigan State University in 1974. He joined TI in 1980, after several years on the faculty of the Physics Department at the University of Virginia. His physics research was on nuclear reactions and was highlighted by the discovery of the Giant Spin-Isospin Resonance in heavy nuclei in 1973 and by pioneering experiments in medium-energy heavy-ion reactions in the late 7’s. His early work at Texas Instruments was on SRAM, DRAM, and NMOS/CMOS device physics and process-flow design. Management responsibilities during his first 10 years at TI included overall CMOS and DRAM device/process technology development as well as advanced lithography R&D. The teams which he led developed the first process flows integrating silicide-clad, lightly-doped-drain, shallow-trench-isolated, CMOS transistors, which were forerunners of all modern sub-micron CMOS devices. Non-planar (doped-face trench) DRAM bit cells were also developed under his leadership.

The MMST Program was a $100M+, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, which developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time (still a world record) for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control. The subsequent commercialization of MMST technologies has had a major impact on semiconductor manufacturing.

Dr. Doering is an IEEE Fellow and Chair of the Semiconductor Manufacturing Technical Committee of the IEEE Electron Devices Society. He is also a Fellow of the American Physical Society (APS) and Chair of the Corporate Associates Advisory Committee of the American Institute of Physics. In addition, he is Chair of the Governing Council of the Nanoelectronics Research Initiative (NRI) consortium. Dr. Doering was a member of the Semiconductor Industry Association (SIA) committee that founded the International Technology Roadmap for Semiconductors (ITRS) and is one of the two U.S. representatives to the International Roadmap Committee, which currently governs the ITRS. He also served on the SIA committees that founded the Focus Center Research Program (FCRP) and NRI consortia of the Semiconductor Research Corporation (SRC) as well as on the APS committee that founded the Forum on Industrial and Applied Physics (FIAP). He is a former member of the SRC Board of Directors, and, overall, has served on 88 industry/university/government boards, advisory committees, and study groups. He has also authored/presented 232 publications and invited papers/talks and has 20 U.S. patents.

Co-charing the special symposium on Nano Electronics & Photonics.

Speaking in the Nano Electronics Devices and Nano Electronics for 2020 and Beyond - NNI Signature Initiative Symposium.

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