Nanoelectronic SET-based core for Network-on-chip architectures

B.S. Pes, J.G. Guimaraes, J.C. da Costa
University of Brasilia - UnB, BR

Keywords: single-electron transistor, network-on-chip, core, nanoelectronic, performance


Nanoelectronics is a very promising step the world of electronics is taking. It is proved to be more efficient than the microelectronic approaches currently in use, mainly in terms of area and energy management. A Single Electron Transistor (SET) differs from the traditional FET (Field Effect Transistor) and BJT (Bipolar Junction Transistor) on the fact that its structure is capable of confining electrons to sufficiently small dimensions, so that the quantization of both their charge and their energy are easily observable, making the SET’s, in an essential way, quantum mechanical devices. A digital module, such as an arithmetic logic unit, completely implemented with SETs has already been proposed and validated by simulation. In this work a completely SET based network-on-chip (NoC) nanoelectronic core, as the one showed in Figure 1, will be proposed and simulated. Furthermore, the performance of a simple NoC architecture based on that nanoelectronic core, as the one showed in Figure 2, will also be evaluated. It will be shown that the SET-based NoC has a promising performance considering parameters such as speed, power consumption and area.