2012 Workshop on

Compact Modeling

Symposium Chair

Xing Zhou
Professor
Nanyang Technological University, Singapore

Symposium Sessions
	Tuesday June 19
10:30	WCM: Workshop on Compact Modeling I
12:30	Networking Lunch - Expo
1:00	WCM: Workshop on Compact Modeling II
3:00	WCM: Workshop on Compact Modeling III
4:30	Expo Reception and Poster Session I (4:30 - 6:30)
	Wednesday June 20
8:30	WCM: Workshop on Compact Modeling IV
10:30	WCM: Workshop on Compact Modeling V
12:30	Networking Lunch - Expo
1:00	NNI - Director’s Networking Session, National Nanotechnology Coordination Office
1:30	Exhibit and Poster Session II
1:00	WCM: Workshop on Compact Modeling VI
2:45	WCM: Workshop on Compact Modeling VII
4:30	WCM: Workshop on Compact Modeling VIII
5:30	TechConnect Innovation Showcase Reception
6:00	CTSI Utility Technology Challenge Awards and Reception
	Thursday June 21
12:30	National Innovation Showcase - Networking Lunch (available for purchase)
4:00	TechConnect National Innovation Showcase, Reception & Poster Session III

Symposium Program
	Tuesday June 19
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10:30	WCM: Workshop on Compact Modeling I	Room 204
	Session chair: Xing Zhou, Nanyang Technological University, SG
10:30	HiSIM-SOTB: A Compact Model for SOI-MOSFET with Ultra-Thin Si-Layer and BOX M. Miura-Mattausch, H. Kikuchihara, U. Feldmann, T. Nakagawa, M. Miyake, T. Iizuka, H.J. Mattausch, Hiroshima University, JP
11:00	Design Methodology for Ultra Low-Power Analog Circuits using Next Generation BSIM 6 Compact Model C.C. Enz, A. Mangla, M.-A. Chalkiadaki, Ecole Polytechnique Fédérale de Lausanne (EPFL), CH
11:30	BSIM6: Symmetric Bulk MOSFET Model Y.S. Chauhan, M.A. Karim, S. Venugopalan, S. Khandelwal, A. Niknejad, C. Hu, University of California, Berkeley, US
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12:30	Networking Lunch - Expo	Expo Hall AB
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1:00	WCM: Workshop on Compact Modeling II	Room 204
	Session chair: Christian Enz, Swiss Center for Electronics and Microtechnology, CH
1:00	Unified Modeling of Multigate MOSFETs Based on Isomorphic Modeling Principles T.A. Fjeldly, U. Monga, Norwegian University of Science and Technology, NO
1:30	A Simplified Model for Dynamic Depletion in Doped UTB-SOI/DG-FinFETs X. Zhou, S.B. Chiah, Nanyang Technological University, SG (bio)
2:00	Analytical Surface Potential Calculation in UTBSOI MOSFET with Independent Back-Gate Control S. Khandelwal, Y.S. Chauhan, M.A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu, Norwegian University of Science & Technlogy, NO
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3:00	WCM: Workshop on Compact Modeling III	Room 204
	Session chair: Tor Fjeldly, Norwegian University of Science and Technology, NO
3:00	Correlated statistical SPICE models for High-Voltage LDMOS Transistors based on TCAD statistics E. Seebacher, A. Steinmair, austriamicrosystemsAG, AT
3:30	Modeling of DMOS Device for High-Voltage Applications Based on 2D Current Flow F. Ueno, A. Tanaka, M. Miyake, T. Iizuka, T. Yamamoto, H. Kikuchihara, H.J. Mattausch, M. Miura-Mattausch, Hiroshima University, JP
4:00	Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation T. Iizuka, K. Fukushima, A. Tanaka, M. Ueno, M. Miura-Mattausch, Hiroshima University, JP
4:30	Unified Regional Approach to High Temperature SOI DC/AC Modeling S.B. Chiah, X. Zhou, Z. Chen, H.M. Chen, Nanyang Technological University, SG
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4:30	Expo Reception and Poster Session I (4:30 - 6:30)	Expo Hall AB
	Wednesday June 20
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8:30	WCM: Workshop on Compact Modeling IV	Room 204
	Session chair: Mitiko Miura-Mattausch, Hiroshima University, JP
8:30	Measurement and Characterization of Interconnect Process Parameters for VLSI Design N. Arora, Silterra, MY
9:00	i-MOS: A Platform for Compact Modeling Sharing H. Wang, M. Chan, HKUST, HK
9:30	Critical review of CNTFET compact models M. Claus, M. Haferlach, D. Gross, M. Schröter, Technische Universität Dresden, DE
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10:30	WCM: Workshop on Compact Modeling V	Room 204
	Session chair: Narain Arora, Silterra, MY
10:30	Hierarchical Memory Modeling for Reliable Integration Y. Cao, Z. Xu, C. Yang, K. Sutaria, C. Chakrabarti, Arizona State University, US
11:00	Leakage current in HfO2 stacks: from physical to compact modeling L. Larcher, A. Padovani, P. Pavan, Università di Modena e Reggio Emilia, IT
11:30	On the Variability of HfOx RRAM: From Numerical Simulation to Compact Modeling X. Guan, S. Yu, H.-S.P. Wong, Stanford University, US
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12:30	Networking Lunch - Expo	Exhibit Hall AB
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1:00	NNI - Director’s Networking Session, National Nanotechnology Coordination Office	Exhibit Hall A
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1:30	Exhibit and Poster Session II	Exhibit Hall AB
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1:00	WCM: Workshop on Compact Modeling VI	Room 204
	Session chair: Michael Schröter, University of Technology Dresden, DE
1:00	Model the AlGaN/GaN High Electron Mobility Transistors Y. Wang, Tsnghua University, CN
1:30	An analytical 2DEG model considering the two lowest subbands J. Zhang, X. Zhou, NTU singapore, SG
2:00	Compact Model for Intrinsic Capacitances in AlGaN/GaN HEMT Devices S. Khandelwal, T.A. Fjeldly, NTNU, NO
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2:45	WCM: Workshop on Compact Modeling VII	Room 204
	Session chair: Mansun Chan, Hong Kong University of Science and Technology, HK
2:45	Modeling of Chain History Effect based on HiSIM-SOI Y. Fukunaga, M. Miyake, A. Toda, K. Kikuchihara, S. Baba, U. Feldmann, H.J. Mattausch, M. Miura-Mattausch, Hiroshima university, JP
3:15	Modeling and Analysis of MOS Capacitor Controlled by Independent Double Gates P.K. Thakur, S. Mahapatra, Indian Institute of Science Bangalore, IN
3:45	Understanding and Modeling Quasi-Static Capacitance-Voltage Characteristics of Organic Thin-Film Transistors C. Ucurum, H. Goebel, Helmut Schmidt University - University of the Federal Armed Forces Hamburg, DE
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4:30	WCM: Workshop on Compact Modeling VIII	Room 204
	Session chair: Yogesh Chauhan, University of California at Berkeley, US
4:30	Discreteness and Distribution of Drain Currents in FinFETs N. Lu, IBM, US
5:00	A Fully Automated Method to Create Monte-Carlo MOSFET Model Libraries for Statistical Circuit Simulations J. Wang, H. Trombley, J. Watts, M. Randall, R. Wachnik, IBM Semiconductor Research and Development Center, US
5:30	Boundary Condition Independence of Cauer RC Ladder Compact Thermal Models M. Janicki, T. Torzewicz, Z. Kulesza, A. Napieralski, Technical University of Lodz, PL
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5:30	TechConnect Innovation Showcase Reception	Expo Hall CD
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6:00	CTSI Utility Technology Challenge Awards and Reception	Expo Theater 1
	Session chair: Patti Glaza, Arsenal Venture Partners, US
	Thursday June 21
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12:30	National Innovation Showcase - Networking Lunch (available for purchase)	Expo Hall CD
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4:00	TechConnect National Innovation Showcase, Reception & Poster Session III	Expo Hall CD

Synopsis

Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:

Intrinsic Models
- Bulk MOSFET
- SOI MOSFET (partial-/full-depletion)
- Multiple-Gate FET (DG/TG/GAA)
- High-Voltage/LDMOS
- Thin-Film Transistor (TFT)
- Schottky-Barrier/Tunneling FET (SB-FET/TFET)
- Bipolar/Junction (BJT/HBT/SiGe/JFET)
- HEMT (GaN/InGaP/InGaAs)
- RF/noise
Extrinsic/Interconnect Models
- Parasitic elements
- Passive device
- Diode
- Resistor
- ESD
- Interconnect
Atomic/Quantum Models
- Ballistic device
- Carbon-Nanotube (CNFET)
- Organic FET
Statistical Models
- Statistical/variability
- Reliability/hot carrier
- Numerical/TCAD/table-based
Multi-Level Models
- Subcircuit model
- Gate/block model
- Behavioral model
Model Extraction and Interface
- Parameter extraction and optimization
- Model-simulator interface
- Model standardization

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Invited Speakers

Invited speakers from all over the world are listed below:

Narain Arora, Silterra, Malaysia
Yu Cao, Arizona State University, USA
Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
Tor Fjeldly, Norwegian University of Science and Technology, Norway
Chenming Hu and Yogesh Chauhan, University of California at Berkeley, USA
Mitiko Miura-Mattausch, Hiroshima University, Japan
Paolo Pavan, Luca Larcher, and Andrea Padovani, Università di Modena e Reggio Emilia, Italy
Michael Schröter, University of Technology Dresden, Germany
Ehrenfried Seebacher, Austriamicrosystems AG, Austria
Yan Wang, Tsinghua University, China
Philip Wong and Ximeng Guan, Stanford University, USA
Xing Zhou, Nanyang Technological University, Singapore

Presentation Slides

Contributed presentation slides. (Click on each to download the PDF file. © Copyright of the PDF files belongs to the respective contributors.)

Download and save the entire ZIP file of presentation slides (27 MB)
Workshop Program

Y.S. Chauhan, BSIM6: Symmetric Bulk MOSFET Model
T. Fjeldly, Unified Modeling of Multigate MOSFETs Based on Isomorphic Modeling Principles
X. Zhou, A Simplified Model for Dynamic Depletion in Doped UTB-SOI/DB-FinFETs
Y.S. Chauhan, Analytical Surface Potential Calculation in UTBSOI MOSFET with Independent Back-Gate Control
X. Zhou, Unified Regional Approach to High Temperature SOI DC/AC Modeling
M. Chan, i-MOS: A Platform for Compact Model Sharing
M. Schröter, Critical review of CNTFET compact models
Y. Cao, Hierarchical Memory Modeling for Reliable Integration
L. Larcher, Leakage Current in HfO₂ Stacks: From Physical to Compact Modeling
X. Zhou, An Analytical 2DEG Model Considering the Two Lowest Subbands
T. Fjeldly, Compact Modeling of Intrinsic Capacitance in AlGaN/GaN HEMT Devices
N. Lu, Discreteness and Distribution of Drain Currents in FinFETs
H. Trombley, A Fully Automated Method to Create Monte Carlo MOSFET Model Libraries for Statistical Circuit Simulations
A. Napieralski, Boundary Condition Independence of Cauer RC Ladder Compact Thermal Models

Web Site Archive

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Journal Submissions

Microelectronics Journal

Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on microelectronics.

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