Linearity evaluation of Silicon Nanowire Surrounding Gate MOSFET for high performance ULSI applications

N. Aggarwal, K. Sikka, I. Gupta, R. Chaujar
Delhi Technological University, IN

Keywords: ATLAS, SNW MOSFET, IIP3, TCAD

Summary:

The inspiration of this work is that the search for high performance ICs has led to scaling of MOSFETs down to sub-50nm regime and thus Silicon Nanowire (SNW) MOSFETs offer a promising solution for realizing CMOS technology. Linearity is an important figure of merit in all RF and wireless applications to guarantee minimum signal distortion in modern communication systems. In this paper, an extensive study on the effect of variation in gate/channel length (Lg) of a novel SNW MOSFET with surrounding gate on linearity evaluation metrics namely VIP2, VIP3, IIP3 and transconductance coefficients: gm1, gm3 has been discussed using ATLAS device simulator. For high linearity and low distortion operation, VIP2, VIP3, IIP3,gm should be high and gm3 should be low. The analysis indicates that linearity of SNW MOSFETs decreases as gate/channel length increases.