Nanotech 2011

Modeling Bias Stress Effect on Threshold Voltage for Amorphous Silicon Thin-Film Transistors

C-H Shen
National Chiao Tung University, TW

Keywords: a-Si:H RPI TFT model, stress time, transfer characteristics, flat band voltage, threshold voltage, amorphous silicon thin-film transistors

Abstract:

Amorphous silicon thin-film transistors (a-Si:H TFTs) are widely used in active-matrix backplanes for LCD displays on glass. Unfortunately, DC and dynamic characteristics of a-Si:H TFTs are sensitive [1]; in particular, they suffer form electric-field-induced threshold voltage shift [2-4]. Fig. 1(a) shows the DC characteristics of fabricated samples w/o stress, where gate length/width = 4 μm/26.5 μm, gate bias (Vgs) = 28 V, drain bias (Vds) = 0 V and temperature (T) = 65oC. We find that the drain current significantly decreases after a prolonged gate bias stress. From transfer characteristics in log scale viewpoint, the subthreshold swing becomes larger after stressing, as shown in Fig. 1(b). The DC characteristic was widely studied and modeled recently; however, the dependence of DC characteristic on bias stress time has not been clear yet. In this study, we model bias stress effect for a-Si:H TFTs in TFT-LCD circuit simulation.
 

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