Nanotech 2010

3-state Quantum Dot Gate FETs in Designing High Sampling Rate ADCs

S. Karmakar, J.A. Chandy, F.C. Jain
University of Connecticut, US

Keywords: ADC, QDFETs, quantum dots, 3-state devices, comparators

Abstract:

In this work we present Cadence simulation of 3-bit Analog-to-Digital Converters (ADCs) based on compact 3-QDFET comparators, using 32nm design rules with BSIM 3.2.0 and BSIM 3.2.4 models [3]. In addition, we present the precise control of the threshold voltage of variable threshold voltage transistor which will remove R-2R ladder problem in conventional analog-to-digital converters(ADCs).
 
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