Nanotech 2010

Wafer Bonding as a Key Technology for 3D Integration of MEMS and Electronics (invited)

M. Wiemer, J. Braeuer, D. Wuensch, T. Gessner
Fraunhofer Research Institution for Electronic NanoSystems, DE

Keywords: MEMS, Packaging, Connectivity, Microintegration, Microassembly


3D Integration is of major interest for several applications in the fields of microelectronics and MEMS (Micro-Electro-Mechanical-Systems) technologies providing the opportunity to integrate electronic devices of different functions and technologies, such as MEMS electronic devices of corresponding electronics and evaluation units. Beside important fabrication processes such as wafer thinning, Through-Silicon-Via (TSV) drilling or etching and TSV filling one well established technology for the fabrication of 3D devices is wafer bonding. Several technologies like direct and anodic bonding without intermediate layer or thermo-compression wafer bonding with intermediate layers like low melting frit glasses, eutectic materials or polymers were developed during the last years and are nowadays extensively used in industrial applications. One critical parameter in wafer level bonding is the process temperature. It should be kept as low as possible. The reasons for this low process temperature are low-melting materials used for vias as well as different coefficients of thermal expansion (CTE) of the bonding partners. The paper gives an overview of different bonding techniques used for MEMS packaging as well as MEMS and electronics integration with special focus on new low temperature bonding techniques presenting their process flow as well as the results like the bond yield and bond strength. In particular, direct silicon and glass bonding has a major advantage within the MEMS packaging because there are no additional intermediate layers like in eutectic or adhesive bonding needed. One possibility for the process temperature reduction is the usage of surface activating procedures prior to bonding, like low-pressure plasma or ion beam treatment. Another opportunity for surface activation is the dielectric barrier discharge (DBD), which offers stable plasma at atmospheric pressure (AP). A significantly increasing in bond strength for the Si/Si bonding interface could be achieved by plasma treatment with process gases nitrogen and synthetic air (80 vol% N2 + 20 vol% O2) (Figure 1). This activation process was followed by rinsing the wafers for 10 minutes in de-ionized water. After the pre-bonding process at room temperature the wafers were annealed at different temperatures, which ranged from 40°C to 200°C. After dicing into single chevron-test structures, the bond strength of the Si/Si interface was characterized by the Micro-Chevron test. As can be seen in Figure 1 for the nitrogen and synthetic air plasma-treated wafer stacks, the bond strength is two or three times higher than the non-activated reference wafer stacks. Furthermore the paper introduces reactive bonding, which is a relatively new joining technique for the mounting of microelectronic components and the hermetic sealing of microelectronic packages. It is based on the use of reactive nano scale multilayer foils, mostly in connection with additional solder layers. The heat used for the bonding process is generated by a self-propagating exothermic reaction within the foil. The reaction is initiated by a small pulse of energy, such as an electrical spark, or a laser impulse (see Figure 2). The decisive advantage of this technology is that the components to be joined are not exposed to high temperatures means that the generated heat is localized to the bonding interface.
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