Microtech 2011

Graphene Nanoelectronics Beyond Current Technological Limitations (invited presentation) a Simulation Perspective

F. Register, D. Basu, X. Mou, D. Reddy, S.K. Banerjee, G. Carpenter, A. Hassabi, A. MacDonald
University of Texas Austin, US

Keywords: grapene, nanoelectronics


Graphene is an emerging material currently being considered for both end-of-the roadmap CMOS applications and beyond CMOS applications. Practical Challenges with the use of graphene include a zero band gap, ambipolar transport, and a host of technological challenges including fabrication of large area graphene and creation of compatible high quality dielectrics and contacts. Yet symmetric electron and hole transport with high carrier mobilities and thermal velocities, mono-atomically thin layers for ultimate electrostatic control, potential for (as compared to use of carbon nanotubes) device definition solely via conventional lithography, and even ambipolar transport continue to draw interest to the material. In this presentation, via select illustrative examples, we look at potential performance benefits and limitations of graphene beyond current experimental limits through simulation for short-channel CMOS and for one particular beyond CMOS device concept, the Bilayer pseudoSpin FET (BiSFET), based on possible room-temperature superfluidity in graphene bilayers via a synergy of graphene properties.

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