Microtech 2011

Trends and Challenges in Compact Modeling – a Foundry Supplier’s Perspective (invited presentation)

S-W. Lee
Semiconductor Manufacturing Internation (Shanghai) Corp., CN

Keywords: compact modeling


Through continued scaling of technology feature size, adoption of new materials, invention of novel device structures and the development of advanced lithography and OPC, the silicon semiconductor industry had successfully met the projection of Moore’s law and this evolution sees no ending in sight. This amazing achievement in process technology resulted in ever increasing number of higher performance and more energy efficient devices available on a per chip basis and has been a fundamental building block that enabled the recent explosion in personal computers, cloud computing, tablet personal computers, smart phones and other exciting applications. Sophisticated schemes in process technology to drive device performance and energy efficiency also resulted in rapidly increased complexity in device behavior that depend not only on its local structure but also the complex surrounding environment. In addition, the expanding market a process technology is targeted to support also demanded an increasing classes of devices it must provide on a given technology node. Another important consequence of the complex dependency in device behavior is a more convoluted relationship between systematic variation in device’s electrical characteristics and process technology parameters. These changes have been driving continued sophistication in compact device models that are no longer ‘compact” with their exploding number of model parameters. To address interconnect delay, energy consumption and cost, advanced 3D integration including TSV for system-level integration will emerge and this will further advance the requirement on compact modeling in the near future. In this talk, the trends in process technology and compact modeling will be summarized and the impact of these trends on compact modeling, device test keys, model characterization, usage of compact models, QA methodology and worst case methodology will be discussed. Further, the impact on the already difficult-to-meet synchronization between process technology development, IP development and stabilized Spice models and design rules to support time-to-market business strategy will also be examined. Finally, this talk will identify new requirements and new opportunities in compact modeling, and discuss potential solutions for some of these challenges.

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