2010 Workshop on
Compact Modeling
June 21 - 25, 2010
Anaheim Convention Center
Anaheim, California, U.S.A.
Workshop Chair
|
Xing Zhou Professor Nanyang Technological University, Singapore |
Symposium Sessions | ||
Tuesday June 22 | ||
Wednesday June 23 | ||
| 8:30 | WCM: SOI/Bulk Models | |
| 10:00 | Networking Coffee Break | |
| 10:30 | WCM: DG MOSFET Models | |
| 1:30 | WCM: GAA MOSFET Models | |
| 3:30 | WCM: RF/Statistical/Atomic/Interconnect Models | |
| 4:00 | Poster Session and TechConnect Expo Reception (4:00 - 6:00) - Expo Hall | |
| 6:00 | TechConnect Innovation Showcase Reception (6:00 - 8:00) - Ballroom 3rd Floor | |
Thursday June 24 | ||
| 10:00 | TechConnect Innovation Showcase Coffee Break - Ballroom 3rd Floor | |
| 5:00 | TechConnect Investment Networking Reception - Second Floor | |
Symposium Program | ||
Wednesday June 23 | ||
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| 8:30 | WCM: SOI/Bulk Models | Room 303 A |
| Session chair: Xing Zhou, Nanyang Technological University, Singapore | ||
| 8:30 | Theory of Bipolar MOSFET (BiFET) with Electrically Short Channels (invited presentation) B.B. Jie, C-T. Sah, Univesity of Florida, US | |
| 9:00 | Impact of Gate-Induced-Drain-Leakage current modeling on circuit simulations in 45nm SOI technology and beyond H. Wang, R. Williams, L. Wagner, J. Johnson, P. Hyde, S. Springer, IBM, US | |
| 9:20 | Modeling of Gate Leakage, Floating Body Effect, and History Effect in 32nm HKMG PD-SOI CMOS Y. Deng, R.A. Rupani, J. Johnson, S. Springer, IBM, US | |
| 9:40 | A Unified Charge-Based Model for SOI MOSFETs Valid from Intrinsic to Heavily Doped Channel J. Zhang, J. He, L. Zhang, X. Zhou, Z. Zhou, Peking University, CN | |
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| 10:00 | Networking Coffee Break | Foyer 2nd Floor |
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| 10:30 | WCM: DG MOSFET Models | Room 303 A |
| Session chair: Bin Jie, USA | ||
| 10:30 | Non-Charge-Sheet Analytic Model for Ideal Retrograde Doping MOSFETs Z. Zhou, J. Zhang, X. Zhou, X. Lin, J. He, Peking University, CN | |
| 10:50 | Subthreshold Quantum Ballistic Current and Quantum Threshold Voltage Modeling for Nanoscale FinFET U. Monga, T.A. Fjeldly, UniK/Norwegian University of Science and Technology, NO | |
| 11:10 | Electrostatic Potential Compact Model for Symmetric and Asymmetric Lightly Doped DG-MOSFET Devices H. Abebe, E. Cumberbatch, S. Uno, V. Tyree, University of Southern California/ISI, US | |
| 11:30 | Analytic Channel Potential Solution of Symmetric DG AMOSFETs L. Chen, Y. Xu, L. Zhang, X. Zhou, W. Zhou, J. He, Peking University, CN | |
| 11:50 | Source/Drain Edge Modeling for DG MOSFET Compact Model T. Nakagawa, S. O’uchi, T. Sekigawa, T. Tsutsumi, M. Hioki, H. Koike, AIST (National Institute of Advanced Industrial Science and Technology), JP | |
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| 1:30 | WCM: GAA MOSFET Models | Room 303 A |
| Session chair: Ning Lu, IBM, US | ||
| 1:30 | Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model X. Zhou, G.J. Zhu, M.K. Srikanth, S.H. Lin, Z.H. Chen, J.B. Zhang, C.Q. Wei, Y.F. Yan, R. Selvakumar, Nanyang Technological University, SG | |
| 1:50 | Analytical Modeling of the Subthreshold Electrostatics of Nanoscale GAA Square Gate MOSFETs S.K. Vishvakarma, T.A. Fjeldly, Norwegian University of Science and Technology, NO | |
| 2:10 | A Continuous Compact Model of Short-Channel Effects for Undoped Cylindrical Gate-All-Around MOSFETs B. Cousin, M. Reyboz, O. Rozeau, M.-A. Jaud, T. Ernst, J. Jomaah, CEA, LETI, MINATEC, FR | |
| 2:30 | Analytical Solution of Surface Potential for Un-Doped Surrounding-Gate MOSFET A. Dey, A. DasGupta, Arizona State University, US | |
| 2:50 | Analytical model of quantum threshold voltage in short-channel nanowire MOSFET including band structure effects J. Dura, S. Martinie, D. Munteanu, M.-A. Jaud, S. Barraud, J.L. Autran, CEA-LETI Minatec, FR | |
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| 3:30 | WCM: RF/Statistical/Atomic/Interconnect Models | Room 303 A |
| Session chair: Xing Zhou, Nanyang Technological University, Singapore | ||
| 3:30 | Bias Dependence of Low Frequency Noise in 90nm CMOS N. Mavredakis, A. Antonopoulos, M. Bucher, Technical University of Crete, GR | |
| 3:50 | Modeling of Mismatch and Across-Chip Variations in Compact Device Models N. Lu, IBM, US | |
| 4:10 | Improved Compact Model of Quantum Sub-band Energy Levels for MOSFET Device Application W. Feldman, E. Cumberbatch, H. Abebe, Unniversity of Southern California/ISI, US | |
| 4:30 | Compact Modeling of Signal Transients for Dispersionless Interconnects With Resistive, Capacitive and Inductive Terminal Loads Chi Liu, Z. Zhou, X. Lin, J. Xia, X. Zhang, J. He, Peking University, CN | |
| 4:50 | Guidelines for Verilog-A Compact Model Coding G. Depeyrot, F. Poullet, dolphin integration, FR | |
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| 4:00 | Poster Session and TechConnect Expo Reception (4:00 - 6:00) - Expo Hall | Expo Hall |
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| 6:00 | TechConnect Innovation Showcase Reception (6:00 - 8:00) - Ballroom 3rd Floor | Ballroom BC |
Thursday June 24 | ||
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| 10:00 | TechConnect Innovation Showcase Coffee Break - Ballroom 3rd Floor | Ballroom BC |
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| 5:00 | TechConnect Investment Networking Reception - Second Floor | Foyer 2nd Floor |
Synopsis
Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.
Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation, which are largely categorized into the following groups:
- Intrinsic Models
- Bulk MOSFET
- SOI MOSFET (partial-/full-depletion)
- Multiple-Gate FET (DG/TG/GAA)
- High-Voltage/LDMOS
- Thin-Film Transistor (TFT)
- Schottky-Barrier/Tunneling FET (SB-FET/TFET)
- Bipolar/Junction (BJT/HBT/SiGe/JFET)
- RF/noise
- Extrinsic/Interconnect Models
- Parasitic elements
- Passive device
- Diode
- Resistor
- ESD
- Interconnect
- Atomic/Quantum Models
- Ballistic device
- Carbon-Nanotube (CNFET)
- Organic FET
- Statistical Models
- Statistical/variability
- Reliability/hot carrier
- Numerical/TCAD/table-based
- Multi-Level Models
- Subcircuit model
- Gate/block model
- Behavioral model
- Model Extraction and Interface
- Parameter extraction and optimization
- Model-simulator interface
- Model standardization
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Journal Submissions
Microelectronics Journal
Published since 1969, Microelectronics Journal is an international forum for the dissemination of research into, and applications of, microelectronics. Papers published in Microelectronics Journal have undergone peer review to ensure originality, relevance and timeliness. The journal thus provides a worldwide, regular and comprehensive update on microelectronics.
For consideration into the Microelectronics Journal please select the “Submit to Microelectronics Journal” button during the on-line submission procedure.
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