Microtech2010 2010

Nano-Electronics and Nano-Spintronics (invited presentation)

K.L. Wang
University of California Los Angeles, US

Keywords: nano-electronics, devices, architecture


Today’s most outstanding challenges of VLSI electronics as identified by ITRS are: power dissipation per chip, variability and the limit of the physical size. We will discuss the options in meeting these challenges through innovative approaches in devices and nanoarchitectures. In device level, we will examine other state variables in addition to the use of electron charge for logic operation, which is represented as voltage or current. In particular, we will discuss the exposé, in that spintronics as a collective effect with an appropriate order parameter such as magnetic moment as a state variable may be considered favorably for a new room-temperature information processing paradigm. Indeed using collective spins or nanomagnets offers the possibility of constructing nonvolatile electronics, which allows for power savings in dynamic switching and during standby, making the energy dissipation at the device level approaching the fundamental limit of the Maxwell’s, Shannon’s and Landaur’s limit. The use of nanomaterials will also make easy to invoke non-equilibrium operations, which may further reduce dynamic power dissipation below the limit. We will show that using dilute magnetic semiconductor (DMS), MnGe, carrier-mediated transition from paramagnetic to ferromagnetic phases by electric-field control is achieved at room temperature. This paves the pathway towards nonvolatile electronics. Likewise at the architecture level, we will show that by placing memory immediately adjacent to logic circuits as in case of CMOL (CMOS at molecular level) and NASIC (nanowire ASIC), the performance may be improved many fold beyond standard CMOS circuits. The use of nonvolatile elements may lead to new architectures for low power applications.
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