Microtech2010 2010

Self-Leveling Two Dimensional Probe Arrays for Dip Pen Nanolithography®

J. Haaheim, V. Val, J. Bussan, S. Rozhok, J-W. Jang, J. Fragala, M. Nelson
NanoInk, US

Keywords: dip-pen nanolithography

Abstract:

Scanning Probe Lithography (SPL) has witnessed a dramatic transformation with the advent of two dimensional probe arrays. Whereas early work with single probes was justifiably assessed as being too slow to practically apply in a nanomanufacturing context, we have recently demonstrated throughputs up to 3×107 µm^2 per hour – in some cases exceeding e-beam lithography (EBL) – using cm^2 arrays of 55,000 tips tailored for Dip Pen Nanolithography® (DPN®). Parallelizing DPN has been critical since there exists a need for a lithographic process that is not only high throughput, but also high resolution (DPN has shown line widths down to 14 nm) with massive multiplexing capabilities. Whereas previous methods required non-trivial user manipulation in order to bring the 2D array level to the substrate, we now demonstrate a self-leveling fixture for NanoInk’s 2D nano PrintArray. When mounted on NanoInk’s NLP 2000, the 55,000 tip array can achieve a planarity of <0.1º with respect to the substrate in a matter of seconds, with no user manipulation required. Additional fine-leveling routines (< 2 minutes of user interaction) can improve this planarity to <0.002º with respect to the substrate – a Z-difference of less than 600 nm across 1 cm^2 of surface area. We herein show highly homogeneous etch-resist nanostructure results patterned from a self-leveled array of DPN pens, with feature size standard deviation of <6% across a centimeter square sample. We illustrate the mechanisms and methods of the operating self-leveling fixture, and detail the advantages thereof. Finally, we emphasize that this methodology brings us closer to the goal of true nanomanufacturing by automating the leveling process, reducing setup time by at least a factor of 10, enhancing the ease of the overall printing process, and ultimately ensuring a more level device with subsequently homogeneous nanostructures.
 
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